chip__ADDC__src___ADDC___49072dbce8/testbench/tb_prompt.txt

You are an expert RTL verification engineer. Generate a single self-contained `tb.py` cocotb script for the Verilog sample below.

Goal:
- Write a practical cocotb testbench that checks the reference RTL passes.
- The testbench does not need perfect coverage, but it must reflect important behaviors described by the prompt.
- Prefer 3-6 focused checks instead of an overly ambitious exhaustive test.

Hard requirements:
- Output only valid Python source code for one file named `tb.py`
- The file must be directly runnable with: `python tb.py`
- Use only Python stdlib + cocotb
- Use `from cocotb_tools.runner import get_runner`
- Use Icarus Verilog as the simulator (`get_runner("icarus")`)
- The script must work from inside the item's `testbench/` directory
- Resolve project paths with `project_root = Path(__file__).resolve().parents[1]`
- Build the DUT from `project_root / "reference" / "top.v"` plus any support files listed below
- Top-level module name is `ADDC`
- If undefined backtick macros are listed below, add build-time `-DNAME=32` defines for them in the runner build args unless you can infer a better small integer value
- Include at least one reset/initialization check if the interface suggests reset exists
- If a signal may or may not exist, guard access with `hasattr(dut, "signal")`
- Avoid external data files, Makefiles, pytest, or shell calls
- Keep the testbench robust and concise

Implementation guidance:
- If there is a clock input, create a cocotb clock.
- If there is a reset input, drive reset first.
- Derive checks from the prompt and visible RTL behavior.
- Prefer checking observable outputs, state-related outputs, or handshake progress.
- If the prompt is vague, test the clearest core behavior visible in the RTL.
- The Python file should contain both the cocotb tests and a `if __name__ == "__main__":` runner section.

## Sample metadata
```json
{
  "task_id": "chip__ADDC__src___ADDC___49072dbce8",
  "split": "train",
  "source_dataset": "lcm-rtl-code-annotations-by-gpt",
  "category": "memory",
  "difficulty": "hard",
  "quality_tier": "compile_only",
  "module_name": "ADDC",
  "prompt_path": "prompt.txt",
  "module_header_path": "module_header.vh",
  "reference_top_path": "reference/top.v",
  "support_file_paths": [],
  "testbench_path": null,
  "compilation_verified": true,
  "simulation_verified": null,
  "metadata": {
    "raw_unit_dir": "/root/autodl-tmp/distill/lcm-dataset/chip/ADPCM_Processor/2.0.SingleResourceMCAC/ADDC/src/_ADDC_",
    "prompt_source": "spec/spec.txt",
    "screen_bucket": "standalone_leaf_hc",
    "prompt_word_count": 260,
    "token_count": 280
  }
}
```

## Source metadata
```json
{
  "item_id": "chip__ADDC__src___ADDC___49072dbce8",
  "raw_path": "/root/autodl-tmp/distill/lcm-dataset/chip/ADPCM_Processor/2.0.SingleResourceMCAC/ADDC/src/_ADDC_",
  "main_v_file": "ADDC.v",
  "prompt_source": "spec/spec.txt",
  "source_dataset": "lcm-rtl-code-annotations-by-gpt"
}
```

## Verify metadata
```json
{
  "compilation_verified": true,
  "simulation_verified": null,
  "compile_log_path": "logs/compile.log",
  "compile_returncode": 0,
  "compile_error_summary": null
}
```

## Undefined macro warnings detected during prior compile
(none observed)

## Natural-language prompt
Module Specification: The ADDC (Adder with carry) module performs operations with two inputs DQ and SEZ, which are 16-bit and 15-bit vectors, respectively, to provide two outputs PK0 and SIGPK depending on the conditions. The module has specific inputs including reset, and clk serving the reset and clock signal purpose respectively. Test signals such as scan_in0 to scan_in4 and scan_enable are used for testing the module, and test_mode helps in transitioning to test conditions. The module outputs consist of PK0, which is determined by the most significant bit from the sum of processed vectors, and SIGPK which is a flag set based on the sum comparison to zero. Scan outputs from scan_out0 to scan_out4 are used for diagnostic and testing. Internally, signals like DQS, DQI, SEZS, SEZI, and DQSEZ are used. DQS is used for snagging the last bit of DQ and DQI relies on DQS comparison with zero. Similarly, SEZS gets the last bit of SEZ, and SEZI is determined by the comparison of SEZS with zero. DQSEZ holds the sum of DQI and SEZI. The module works in stages, with initial stages for assigning values to internal signals DQS, DQI, SEZS, SEZI based on checks and operations applied to the inputs. The next stage performs the addition operation to yield DQSEZ. The final stage assigns PK0 depending upon the most significant bit from the computed sum (DQSEZ) and compares the computed sum to zero to output SIGPK. Thus, the module works as an organized ADDC processor performing the addition operation with intermediate bitwise manipulations and checks.

## Module header
```verilog
module ADDC (
           reset,
           clk,
           scan_in0,
           scan_in1,
           scan_in2,
           scan_in3,
           scan_in4,
           scan_enable,
           test_mode,
           scan_out0,
           scan_out1,
           scan_out2,
           scan_out3,
           scan_out4,
           DQ,
           SEZ,
           PK0,
           SIGPK           
       );
```

## Main RTL
```verilog
/*

Descrition : Get sign of addition of quantized difference signal & partial
	signal estimate

Author : Siddharth Ramkrishnan

Revision History :
//----------------------------------------------------------------------------------
2/12/16	-	Siddharth	- Initial creation
2/15/16	-	Siddharth	- Removal of Variable Size of DQ & Changes to improve Test Coverage
2/17/16	-	Adam		- Added actual description of block
3/30/16	-	Siddharth	- Addition of comments to the (already easy to read) operations
//----------------------------------------------------------------------------------

*/

module ADDC (
           reset,
           clk,
           scan_in0,
           scan_in1,
           scan_in2,
           scan_in3,
           scan_in4,
           scan_enable,
           test_mode,
           scan_out0,
           scan_out1,
           scan_out2,
           scan_out3,
           scan_out4,
           DQ,
           SEZ,
           PK0,
           SIGPK           
       );

input
    reset,                      // system reset
    clk;                        // system clock

input
    scan_in0,                   // test scan mode data input
    scan_in1,                   // test scan mode data input
    scan_in2,                   // test scan mode data input
    scan_in3,                   // test scan mode data input
    scan_in4,                   // test scan mode data input
    scan_enable,                // test scan mode enable
    test_mode;                  // test mode 

output
    scan_out0,                  // test scan mode data output
    scan_out1,                  // test scan mode data output
    scan_out2,                  // test scan mode data output
    scan_out3,                  // test scan mode data output
    scan_out4;                  // test scan mode data output

input [15:0]
	DQ;

input [14:0]
	SEZ;
        
output wire
	PK0,
	SIGPK;

wire
	DQS,
	SEZS;

wire [15:0] 
	DQI,
	DQSEZ,
	SEZI;
	
assign	DQS	=	DQ[15];							// Read the sign of DQ and update to DQS

assign	DQI	=	(DQS == 0)?	DQ	:	(65536 - (DQ & 32767));	// Conversion of Sign Magnitude Number to 2's complement

assign	SEZS	=	SEZ[14];						// Read the sign of SEZ and update to SEZS
	
assign	SEZI	=	(SEZS == 0)?	SEZ	:	((32768) + SEZ);	// Conversion of 15 bit 2's complement to 16 bit representation
	
assign	DQSEZ	=	(DQI + SEZI);						// 2's complement addition of DQ and SEZ
	
assign	PK0	=	DQSEZ[15]; 						// Read the sign of DQSEZ and update to PK0
	
assign	SIGPK	=	(DQSEZ == 0);						// Zero value status of DQSEZ is indicated in SIGPK

endmodule // ADDC

```

## Support RTL files
(none)