task_id stringclasses 6
values | description stringclasses 6
values | rtl_code stringclasses 6
values | testbench stringclasses 6
values | auxiliary_files dict |
|---|---|---|---|---|
Q1_LBP | # Human-Readable Spec (LBP Accelerator)
## 1. Goal & Scope
Design an RTL hardware module **LBP** that:
* Reads an **8-bit** grayscale image from a host memory interface (**gray\_mem**, 128×128, linear address 0…16383).
* Computes **Local Binary Pattern (LBP)** for every pixel independently using a **3×3, 8-neighbor*... | `timescale 1ns/10ps
module TOP ( clk, rst, gray_addr, gray_req, gray_ready, gray_data, lbp_addr, lbp_valid, lbp_data, finish);
input clk;
input rst;
// ask data
output reg gray_req;
output reg [13:0] gray_addr;
input gray_ready;
input [7:0] gray_data;
// write data
output reg [13:0] lbp_a... | `timescale 1ns/10ps
`define CYCLE 10 // Modify your clock period here
`define End_CYCLE 10000000 // Modify cycle times once your design need more cycle times!
`define PAT "./00_TB/pattern1.dat"
`define EXP "./00_TB/golden1.dat"
module test;
parameter N_EXP = 1... | {
"golden1.dat": "00 //Pixel 0: 000\n00 //Pixel 1: 000\n00 //Pixel 2: 000\n00 //Pixel 3: 000\n00 //Pixel 4: 000\n00 //Pixel 5: 000\n00 //Pixel 6: 000\n00 //Pixel 7: 000\n00 //Pixel 8: 000\n00 //Pixel 9: 000\n00 //Pixel 10: 000\n00 //Pixel 11: 000\n00 //... |
Q2_GEMM |
---
# Human-Readable I/O-Only Spec — `systolic`
## 1) Module
* **Name**: `TOP`
* **Clock**: `clk`, rising-edge.
* **Reset**: `rst`, **Synchronous, active-high**.
* While `rst=1`: internal state is cleared; `o_valid=0`;
* On `rst` deassert (1→0): module is ready to accept a new tile per the rules below.
> All ... | // no multi-dimensional arrays
module TOP (
input clk,
input rst,
input tile_en,
input [15:0] tileA_data_0,
input [15:0] tileA_data_1,
input [15:0] tileA_data_2,
input [15:0] tileA_data_3,
input [15:0] tileB_data_0,
input [15:0] tileB_data_1,
input [15:0] tileB_data_2,
inp... | `timescale 1ns/10ps
`define CYCLE 4.4
`define MAX_CYCLE 5000
`define RST_DELAY `CYCLE/2
`define Matrix1_A_ref "./00_TB/data/matrix1_A.hex"
`define Matrix2_A_ref "./00_TB/data/matrix2_A.hex"
`define Matrix3_A_ref "./00_TB/data/matrix3_A.hex"
`define Matrix1_B_ref "./00_TB/data/matrix1_B.hex"
`define Matrix2_B_ref "./... | {
"golden1.dat": null,
"pattern1.dat": null,
"data/matrix2_O.hex": "0f01\nf269\n1cfe\n1e4a\n035d\n1da1\ne86f\n7438\ncf69\necee\nbeb1\ne2c4\nfcb0\n4d6c\nf23d\n32b8\n7fff\n7589\n12f0\n27eb\nc76b\n7fff\nefb8\n379a\n7384\nb475\nd8c6\n8000\n895d\n5b72\n49ce\n4af0\n1905\n4bf8\n66f7\n8000\n1422\n16c5\nb209\nc922\n5acd\n... |
Q3_CONV |
---
# Version A — Human-Readable Spec (CONV)
## 1) Goal & Scope
Implement module **`TOP`** that:
* Reads a **64×64** grayscale image from the testfixture via the `iaddr/idata` interface. Pixel data width is **20 bits (Q4.16)**.  
* Produces:
1. **Layer 0**: **zero-padding(1) → 3×3 convolution (Kernel 0) → ... | module TOP(
input clk,
input rst,
output reg busy,
input ready,
output reg[11:0] iaddr,
input signed[19:0] idata,
output reg cwr,
output reg[11:0] caddr_wr,
output reg[19:0] cdata_wr,
output reg crd,
output reg[11:0] caddr_rd,
input [19:0] cdata_rd,
output reg[2:0] csel
);
//=====... | `timescale 1ns/10ps
`define CYCLE 10.0 // Modify your clock period here
`define End_CYCLE 100000000 // Modify cycle times once your design need more cycle times!
`define PAT "./00_TB/dat_grad/cnn_sti.dat" // Modify your "dat" directory path
`define L0_EXP0 ... | {
"golden1.dat": null,
"pattern1.dat": null,
"data/matrix2_O.hex": null,
"data/matrix3_O.hex": null,
"data/matrix1_B.hex": null,
"data/matrix1_A.hex": null,
"data/matrix2_A.hex": null,
"data/matrix1_O.hex": null,
"data/inst.hex": null,
"data/matrix2_B.hex": null,
"data/matrix3_B.hex": null,
"dat... |
Q4_HC |
---
# Human Version — Huffman Coding Hardware: Complete Design Specification
## 1) Problem Description
Design and implement a hardware **Huffman Coding generator** (`huffman` core) for lossless compression. The input is a stream of grayscale pixels. For this contest, pixels are restricted to **six symbols** A1..A6 ... | module TOP (
input clk,
input rst,
output [2:0] W,
output [2:0] J,
input [6:0] Cost,
output reg [3:0] MatchCount,
output reg [9:0] MinCost,
output Valid );
//================================================================
// integer / genvar / parameters
//==========================================================... | `timescale 1ns/10ps
`define CYCLE 10.0
`define End_CYCLE 1000000
`define PAT "./00_TB/cost_rom"
`ifdef P1
`define PAT_NUM 1
`elsif P2
`define PAT_NUM 2
`elsif P3
`define PAT_NUM 3
`else
`define PAT_NUM 1
`endif
module test;
integer fd;
localparam LINE_MAX = 256;
integer charcount;... | {
"golden1.dat": null,
"pattern1.dat": null,
"data/matrix2_O.hex": null,
"data/matrix3_O.hex": null,
"data/matrix1_B.hex": null,
"data/matrix1_A.hex": null,
"data/matrix2_A.hex": null,
"data/matrix1_O.hex": null,
"data/inst.hex": null,
"data/matrix2_B.hex": null,
"data/matrix3_B.hex": null,
"dat... |
Q5_JAM |
---
# Human Version — Job Assignment Machine (JAM): Complete Design Specification
## 1) Problem Overview
Implement a hardware **Job Assignment Machine (JAM)** that, for **n = 8** workers and **8** jobs, **exhaustively enumerates all assignments** (permutations) to:
1. find the **minimum total cost**, and
2. report... |
module TOP(clk, rst, gray_data, gray_valid, CNT_valid, CNT1, CNT2, CNT3, CNT4, CNT5, CNT6,
code_valid, HC1, HC2, HC3, HC4, HC5, HC6, M1, M2, M3, M4, M5, M6);
input clk;
input rst;
input gray_valid;
input [7:0] gray_data;
output reg CNT_valid;
output [7:0] CNT1, C... |
`timescale 1ns/10ps
`define CYCLE 10 // clk period. DO NOT modify period
`define tb1
`ifdef tb1
`define PAT "./00_TB/pattern1.dat"
`define EXP "./00_TB/golden1.dat"
`endif
`ifdef tb2
`define PAT "./00_TB/pattern2.dat"
`define EXP "./00_TB/golden2.dat"
`endif
`ifdef tb3
`define PAT "./00_TB/p... | {
"golden1.dat": "03 // CNT1\n06 // CNT2\n02 // CNT3\n33 // CNT4\n0D // CNT5\n19 // CNT6\n1E // HC1\n0E // HC2\n1F // HC3\n00 // HC4\n06 // HC5\n02 // HC6\n1F // M1\n0F // M2\n1F // M3\n01 // M4\n07 // M5\n03 // M6\n\n",
"pattern1.dat": "4\n6\n4\n5\n4\n4\n6\n4\n3\n4\n4\n4\n4\n6\n... |
Q6_DT |
# Human Version — Distance Transform (DT): Complete Design Specification
## 1) Problem Description
Design a hardware **Distance Transform (DT)** engine that reads a **binary 128×128 image** from a host **input ROM (`sti_ROM`)**, computes an **8-distance (chessboard) transform**, and writes the resulting **8-bit gray... | module TOP(
input clk,
input rst,
output reg done ,
output sti_rd ,
output reg [9:0] sti_addr ,
input [15:0] sti_di,
output res_wr ,
output res_rd ,
output reg [13:0] res_addr ,
output reg [7:0] res_do,
input [7:0] res_di
);
integer i;
reg [15:0] idata_buf;
reg [3:0] dup_cnt;
reg [2:0] cnt_c... | `timescale 1ns/10ps
`define CYCLE 8.0 // Modify your clock period here
`define End_CYCLE 100000000 // Modify cycle times once your design need more cycle times!
`define TB1
`ifdef TB1
`define PAT "./00_TB/dat/Geometry_sti.dat"
`define FWEXP "./00_TB/dat/Geometry_fwex... | {
"golden1.dat": null,
"pattern1.dat": null,
"data/matrix2_O.hex": null,
"data/matrix3_O.hex": null,
"data/matrix1_B.hex": null,
"data/matrix1_A.hex": null,
"data/matrix2_A.hex": null,
"data/matrix1_O.hex": null,
"data/inst.hex": null,
"data/matrix2_B.hex": null,
"data/matrix3_B.hex": null,
"dat... |
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