Datasets:
Tasks:
Text Generation
Modalities:
Text
Formats:
json
Sub-tasks:
language-modeling
Languages:
code
Size:
100K - 1M
License:
repo_name stringlengths 6 79 | path stringlengths 5 236 | copies stringclasses 54
values | size stringlengths 1 8 | content stringlengths 0 1.04M ⌀ | license stringclasses 15
values |
|---|---|---|---|---|---|
dh1dm/q27 | src/vhdl/PoC/arith/arith_counter_free.vhdl | 2 | 2946 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module: Poc.arith_counter_free
--
-- Authors: Thomas B. Preusser... | agpl-3.0 |
dh1dm/q27 | src/vhdl/queens/queens_slice.vhdl | 1 | 8378 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 |
dh1dm/q27 | src/vhdl/queens/unframe.vhdl | 1 | 6282 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 |
UnofficialRepos/OSVVM | ResolutionPkg.vhd | 1 | 16067 | --
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@SynthWorks.com
-- Contributor(s):
-- Jim Lewis email: jim@SynthWorks.com
--
-- Package Defines
-- resolved resolution functions f... | artistic-2.0 |
hterkelsen/mal | vhdl/step6_file.vhdl | 13 | 10297 | entity step6_file is
end entity step6_file;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step6_file is
shared variable repl_env: env_ptr;
procedure mal_READ(str: ... | mpl-2.0 |
hterkelsen/mal | vhdl/stepA_mal.vhdl | 11 | 17057 | entity stepA_mal is
end entity stepA_mal;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of stepA_mal is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in ... | mpl-2.0 |
foresterre/mal | vhdl/step6_file.vhdl | 13 | 10297 | entity step6_file is
end entity step6_file;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step6_file is
shared variable repl_env: env_ptr;
procedure mal_READ(str: ... | mpl-2.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/tg_status.vhd | 20 | 5700 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... | cc0-1.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/example_design/rtl/memc1_wrapper.vhd | 2 | 47712 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... | cc0-1.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/wr_data_gen.vhd | 20 | 18946 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... | cc0-1.0 |
qu1x/fsio | src/lib/fsio_put.vhd | 1 | 1412 | -- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <n3vu0r@qu1x.org>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 Novem... | agpl-3.0 |
chastell/art-decomp | kiss/opus_nov.vhd | 1 | 3496 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity opus_nov is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(5 downto 0)
);
end opus_nov;
architecture behaviour of opus_nov is
constant init0: std_logic_vector(3 downto 0) :=... | agpl-3.0 |
chastell/art-decomp | kiss/ex6_rnd.vhd | 1 | 4231 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_rnd;
architecture behaviour of ex6_rnd is
constant s1: std_logic_vector(2 downto 0) := "101"... | agpl-3.0 |
chastell/art-decomp | kiss/dk16_jed.vhd | 1 | 12212 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk16_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk16_jed;
architecture behaviour of dk16_jed is
constant state_1: std_logic_vector(4 downto 0) ... | agpl-3.0 |
chastell/art-decomp | kiss/dk512_hot.vhd | 1 | 4742 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_hot is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_hot;
architecture behaviour of dk512_hot is
constant state_1: std_logic_vector(14 downto... | agpl-3.0 |
chastell/art-decomp | kiss/sse_jed.vhd | 1 | 6957 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_jed;
architecture behaviour of sse_jed is
constant st11: std_logic_vector(3 downto 0) := "00... | agpl-3.0 |
chastell/art-decomp | kiss/dk27_nov.vhd | 1 | 2406 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_nov;
architecture behaviour of dk27_nov is
constant START: std_logic_vector(2 downto 0) :=... | agpl-3.0 |
chastell/art-decomp | kiss/s27_jed.vhd | 1 | 3869 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_jed is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_jed;
architecture behaviour of s27_jed is
constant s000: std_logic_vector(2 downto 0) := "11... | agpl-3.0 |
chastell/art-decomp | kiss/lion_jed.vhd | 1 | 1832 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion_jed;
architecture behaviour of lion_jed is
constant st0: std_logic_vector(1 downto 0) := "... | agpl-3.0 |
chastell/art-decomp | kiss/shiftreg_nov.vhd | 1 | 2558 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftreg_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end shiftreg_nov;
architecture behaviour of shiftreg_nov is
constant st0: std_logic_vector(2 do... | agpl-3.0 |
End of preview. Expand in Data Studio
Dataset Card for AI-HDLCoder
Dataset Description
The GitHub Code dataset consists of 100M code files from GitHub in VHDL programming language with extensions totaling in 1.94 GB of data. The dataset was created from the public GitHub dataset on Google BiqQuery at Anhalt University of Applied Sciences.
Considerations for Using the Data
The dataset is created for research purposes and consists of source code from a wide range of repositories. As such they can potentially include harmful or biased code as well as sensitive information like passwords or usernames.
Languages
{
"VHDL": [".vhdl",".vhd" ]
}
Dataset Structure
Data Instances
{
"repo_name": "sebgod/linguist",
"path": "samples/VHDL/foo.vhd",
"copies": "91",
"size": "217",
"content": "-- VHDL example file\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity inverter is\n\tport(a : in std_logic;\n\t b : out std_logic);\nend entity;\n\narchitecture rtl of inverter is\nbegin\n\tb \u003c\u003d not a;\nend architecture;\n",
"license": "mit"
}
Data Fields
| Field | Type | Description |
|---|---|---|
| content | string | content of source file |
| repo_name | string | name of the GitHub repository |
| path | string | path of file in GitHub repository |
| license | string | license of GitHub repository |
| size | int | size of source file in bytes |
Data Splits
The dataset contains a train split only
Licensing Information
[
'agpl-3.0',
'artistic-2.0',
'mpl-2.0',
'cc0-1.0',
'mit',
'gpl-2.0',
'gpl-3.0',
'lgpl-3.0',
'apache-2.0',
'bsd-3-clause'
]
v1.0
- Initial release of dataset
- The query was executed on 21.07.2023, 00:02:38 UTC+2
- Downloads last month
- 5