id stringlengths 2 23 | desc stringlengths 454 5.31k | testbench listlengths 2 5 | verified stringlengths 250 5.21k |
|---|---|---|---|
fixed_point_adder | Implement a module of a parameterized fixed-point adder for arithmetic operations with fixed precision.
Module name:
fixed_point_adder
Input parameters:
Q: Number of fractional bits (precision). Default to 15.
N: Total number of bits, including integer and fractional parts. Default to 32.
... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n // Parameters\n parameter Q = 15;\n parameter N = 32;\n\n // Inputs\n reg [N-1:0] a;\n reg [N-1:0] b;\n\n // Output\n wire [N-1:0] c;\n reg [N-1:0] expected_result;\n integer error = 0;\n\n fixed_point_adder #(.Q(Q), .N(N... | module fixed_point_adder #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] c
);
reg [N-1:0] res;
assign c = res;
always @(a,b) begin
// both negative or both positive
if(a[N-1] == b[N-1]) begin ... |
adder_16bit | Implement a module of a 16-bit full adder in combinational logic.
Module name:
adder_16bit
Input ports:
a[15:0]: 16-bit input operand A.
b[15:0]: 16-bit input operand B.
Cin: Carry-in input.
Output ports:
y[15:0]: 16-bit output representing the sum of A and B.
Co: Carry-out out... | [
{
"content": "`timescale 1ns/1ps\n\nmodule add16_tb();\n\n reg [15:0] a;\n reg [15:0] b;\n reg Cin;\n\n wire [15:0] y;\n wire Co;\n\n wire [16:0] tb_sum;\n wire tb_co;\n\n assign tb_sum = a + b;\n assign tb_co = tb_sum[16];\n\n integer i;\n integer error = 0;\n\n initial begi... | module adder_16bit (
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
wire Co_temp;
add8 add8_inst1 (
.a(a[15:8]),
.b(b[15:8]),
.Cin(Co_temp),
.y(y[15:8]),
.Co(Co)
);
add8 add8_inst2 (
... |
multi_booth_8bit | Implement an 8-bit Radix-4 booth multiplier that performs the multiplication of two 8-bit inputs (a and b) using the Booth algorithm. It utilizes a clock signal (clk), and a reset signal (reset), and provides the product output (p) and a ready signal (rdy). The ready signal (rdy) is set to 1 to indicate the completion ... | [
{
"content": "`timescale 1ns/1ns\n`define width 8\n`define TESTFILE \"test_data.dat\"\n\nmodule booth4_mul_tb () ;\n reg signed [`width-1:0] a, b;\n reg clk, reset;\n\n wire signed [2*`width-1:0] p;\n wire rdy;\n\n integer total, err;\n integer i, s, fp, numtests;\n\n ... | `timescale 1ns / 1ps
module multi_booth_8bit (p, rdy, clk, reset, a, b);
input clk, reset;
input [7:0] a, b;
output [15:0] p;
output rdy;
reg [15:0] p;
reg [15:0] multiplier;
reg [15:0] multiplicand;
reg rdy;
reg [4:0] ctr;
always @(posedge clk or posedge reset) begin
if (reset)
... |
sequence_detector | Implement a module of a sequence detector to detect a specific 4-bit binary sequence 1001.
Module name:
sequence_detector
Input ports:
clk: Clock signal to synchronize the detector.
rst_n: Reset signal to initialize the state machine.
data_in: 1-bit binary input signal to feed the bitstream for sequen... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule tb_sequence_detector();\n\n reg clk, rst_n, data_in;\n wire sequence_detected;\n\n sequence_detector dut (\n .clk(clk),\n .rst_n(rst_n),\n .data_in(data_in),\n .sequence_detected(sequence_detected)\n );\n integer error = 0; ... | module sequence_detector(
input clk,
input rst_n,
input data_in,
output sequence_detected
);
parameter IDLE = 5'b00001;
parameter S1 = 5'b00010;
parameter S2 = 5'b00100;
parameter S3 = 5'b01000;
parameter S4 = 5'b10000; ... |
comparator_4bit | Implement a module of a 4-bit comparator with multiple bit-level comparators in combinational logic.
Module name:
comparator_4bit
Input ports:
A [3:0]: First 4-bit input operand (binary number to compare).
B [3:0]: Second 4-bit input operand (binary number to compare).
Output ports:
A_... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n\n reg [3:0] A; // Input A (4 bits)\n reg [3:0] B; // Input B (4 bits)\n wire A_greater; \n wire A_equal; \n wire A_less; \n integer i; \n integer error = 0; \n\n comparator_4bit uut (\n .A... | module comparator_4bit(
input [3:0] A, // First 4-bit input operand
input [3:0] B, // Second 4-bit input operand
output A_greater,
output A_equal,
output A_less
);
wire [3:0] diff;
wire cout;
assign {cout, diff} = A - B;
// A > B: if there's no borrow and the... |
width_8to16 | Implement a data width conversion circuit that converts 8-bit data input to 16-bit data output. The module provides two output ports: valid_out, which indicates the validity of the output data, and data_out, which represents the converted 16-bit output data. The first arriving 8-bit data should be placed in the higher ... | [
{
"content": "`timescale 1ns/1ns\nmodule testbench();\n reg rst,valid_in;\n reg clk=1;\n reg[7:0] data_in;\n wire valid_out;\n wire [15:0] data_out;\n\nwidth_8to16 dut(\n .clk (clk),\n .rst_n(rst),\n .valid_in(valid_in),\n .data_in(data_in),\n .valid_out(valid_out),\n .data_out(... | `timescale 1ns/1ns
module width_8to16(
input clk ,
input rst_n ,
input valid_in ,
input [7:0] data_in ,
output reg valid_out,
output reg [15:0] data_out
);
reg [7:0] ... |
edge_detect | Implement a module for edge detection. There is a slowly changing 1-bit signal a. When "a" changes from 0 to 1, the indicating signal rise is 1. When "a" changes from 1 to 0, the falling edge of signal a is shown, the indicating signal down is 1. rise or down will be set to 1 on the next clock when the corresponding ed... | [
{
"content": "`timescale 1ns/1ns\n\nmodule testbench;\n reg clk;\n reg rst_n;\n reg a;\n wire rise;\n wire down;\n\n edge_detect dut (\n .clk(clk),\n .rst_n(rst_n),\n .a(a),\n .rise(rise),\n .down(down)\n );\n\n integer error=0;\n initial begin\n ... | `timescale 1ns/1ns
module edge_detect(
input clk,
input rst_n,
input a,
output reg rise,
output reg down
);
reg a0;
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
rise <= 1'b0;
down <= 1'b0;
end
else begin
if(a &... |
ROM | A Read-Only Memory (ROM) module designed for storing fixed data. This module provides a way to access predefined data based on an 8-bit address input.
Module name:
ROM
Input ports:
addr [7:0]: 8-bit address input used to select the data location in memory.
Output ports:
dout [15:0]: 16-bit output that de... | [
{
"content": "module rom_tb;\n\n reg [7:0] addr_tb; // Address input for the ROM\n wire [15:0] dout_tb; // Data output from the ROM\n\n ROM rom_inst (\n .addr(addr_tb),\n .dout(dout_tb)\n );\n\n integer error;\n\n initial begin\n // Initialize simulation\n ... | module ROM (
input wire [7:0] addr, // 8-bit Address input
output reg [15:0] dout // 16-bit Data output
);
// Declare a memory array of 256 locations, each 16 bits wide, initialized with fixed data
reg [15:0] mem [0:255];
// Initial block to initialize the ROM with data
initial b... |
JC_counter | Implement a 64-bit Johnson counter (torsional ring counter), and the state of the similar 4-bit Johnson counter example is as follows: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000.
Module name:
JC_counter
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-... | [
{
"content": "`timescale 1ns/1ns\n\nmodule testbench;\n\n // Parameters\n parameter CLK_PERIOD = 10; // Clock period in simulation time units\n \n // Inputs\n reg clk;\n reg rst_n;\n \n // Outputs\n wire [63:0] Q;\n\n // Instantiate the module\n JC_counter uut (\n .clk(cl... | `timescale 1ns/1ns
module JC_counter(
input clk ,
input rst_n,
output reg [63:0] Q
);
always@(posedge clk or negedge rst_n)begin
if(!rst_n) Q <= 'd0;
else if(!Q[0]) Q <= {1'b1, Q[63 : 1]};
else Q <= {1'b0, Q[63 : 1]};
end
endmodule
|
pulse_detect | Implement a module for pulse detection. The 1-bit input signal data_in is a continuous input, which is triggered by clk. When "data_in" changes from 0 to 1 to 0(3 cycles), this is considered as a "pulse". The indicating signal dataout is 1 at the end cycle of the "pulse", and then returns to 0 until the corresponding p... | [
{
"content": "`timescale 1ns/1ns\n\nmodule pulse_detect_tb;\n reg clk;\n reg rst_n;\n reg data_in;\n wire data_out;\n\n // Instantiate the DUT (Design Under Test)\n pulse_detect dut (\n .clk(clk),\n .rst_n(rst_n),\n .data_in(data_in),\n .data_out(data_out)\n );\n\n // Generate clock\n initi... | `timescale 1ns/1ns
module pulse_detect(
input clk,
input rst_n,
input data_in,
output reg data_out
);
parameter s0 = 2'b00; // initial
parameter s1 = 2'b01; // 0, 00
parameter s2 = 2'b10; // 01
parameter s3 = 2'b11; // 010
reg [1:0] pulse_level1, pulse_level2;
always @(posedge clk or negedge rst... |
adder_8bit | Implement a module of an 8-bit adder with multiple bit-level adders in combinational logic.
Module name:
adder_8bit
Input ports:
a[7:0]: 8-bit input operand A.
b[7:0]: 8-bit input operand B.
cin: Carry-in input.
Output ports:
sum[7:0]: 8-bit output representing the sum of A and B.... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n \n reg [7:0] a;\n reg [7:0] b;\n reg cin;\n wire [7:0] sum;\n wire cout;\n \n integer i; // Declare the loop variable here\n integer fail_count;\n integer error = 0;\n \n // Instantiate the module\n adder_8bit uut (\n .a(a), \n .b(b), ... | module adder_8bit(
input [7:0] a, b,
input cin,
output [7:0] sum,
output cout);
wire [8:0] c;
full_adder FA0 (.a(a[0]), .b(b[0]), .cin(cin), .sum(sum[0]), .cout(c[0]));
full_adder FA1 (.a(a[1]), .b(b[1]), .cin(c[0]), .sum(sum[1]), .cout(c[1]));
full_adder FA2 (.a(a[2]), .b(b[2])... |
traffic_light | Implement a traffic light, with red, yellow and green three small indicators and a pedestrian button, under normal circumstances, the motor vehicle lane indicator light according to 60 clock cycles of green, 5 clock cycles of yellow, 10 clock cycles of red. When the pedestrian button is pressed, if the remaining green ... | [
{
"content": "`timescale 1ns/1ns\n\nmodule tb_traffic_light;\n \n reg clk;\n reg rst_n;\n reg pass_request;\n wire [7:0] clock;\n wire red;\n wire yellow;\n wire green;\n integer i;\n // Instantiate the module\n traffic_light uut (\n .clk(clk), \n .rst_n(rst_n),\n .pass_request(pass_request)... | `timescale 1ns/1ns
module traffic_light
(
input rst_n,
input clk,
input pass_request,
output wire[7:0]clock,
output reg red,
output reg yellow,
output reg green
);
parameter idle = 2'd0,
s1_red = 2'd1,
s2_yel... |
serial2parallel | Implement a series-parallel conversion circuit. It receives a serial input signal "din_serial" along with a control signal "din_valid" indicating the validity of the input data. The module operates on the rising edge of the clock signal "clk" and uses a synchronous design. The input din_serial is a single-bit data, and... | [
{
"content": "module tb();\n reg clk,rst_n;\n reg din_serial,din_valid;\n wire dout_valid;\n wire[7:0]dout_parallel;\n \nalways #5 clk = ~clk;\ninteger error = 0;\ninitial begin\n clk <= 1'b0;\n rst_n <= 1'b0;\n #12\n rst_n <= 1'b1;\n din_valid <= 1'b1;\n\n din_serial <= 1'b1; #1... |
module serial2parallel(
input clk,
input rst_n,
input din_serial,
input din_valid,
output reg [7:0]dout_parallel,
output reg dout_valid
);
reg[7:0]din_tmp;
reg[3:0]cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt <= 0;
else if(din_vali... |
asyn_fifo | Implement an asynchronous FIFO, FIFO bit width and depth can be configured(parameter DEPTH = 16, parameter WIDTH = 8). The asynchronous FIFO structure is divided into several parts. The first part is dual-port RAM, which is used for data storage. Instantiate dual-port RAM as a submodule, The RAM ports are input wclk, i... | [
{
"content": "01\n01\nab\nab\nac\nac\nad\nad\nae\nae\naf\naf\nb0\nb0\nb1\nb1\nb2\nb2\nb3\nb3\nb4\nb4\nb5\nb5\nb6\nb6\nb7\nb7\nb8\nb8\nb9\nb9\n01\n01\n01\n01\nab\nab\nac\nac\nad\nad\nae\nae\naf\naf\nb0\nb0\n",
"name": "tdata.txt"
},
{
"content": "0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n... | `timescale 1ns/1ns
/***************************************RAM*****************************************/
module dual_port_RAM #(parameter DEPTH = 16, parameter WIDTH = 8)
(
input wclk ,
input wenc ,
input [$clog2(DEPTH)-1:0] waddr ,
input [WIDTH-1:0] wdata ,
input rclk ,
input ... |
RAM | Implement a dual-port RAM with a depth of 8 and a bit width of 6 bits, with all data initialized to 000000. It has two groups of ports, respectively for reading data and writing data, and read and write operations can be carried out at the same time. When the read_en signal is 1, the read_data of the corresponding posi... | [
{
"content": "`timescale 1ns/1ns\n\nmodule tb_RAM;\n\n // Parameters\n parameter CLK_PERIOD = 10; // Clock period in simulation time units\n \n // Inputs\n reg clk;\n reg rst_n;\n reg write_en;\n reg [7:0] write_addr;\n reg [5:0] write_data;\n reg read_en;\n reg [7:0] read_addr;... | module RAM (
input clk,
input rst_n,
input write_en,
input [7:0]write_addr,
input [5:0]write_data,
input read_en,
input [7:0]read_addr,
output reg [5:0]read_data
);
//defination
reg [7 : 0] RAM [11:0];
//output
integer i;
always@(posedge clk or negedg... |
counter_12 | Implement a module of a counter design that requires counting from 4 'b0000 to 4' d11. The counting can be controlled by the input signal valid_count. That is, the count is paused if valid_count is 0. The counter increments on each clock cycle when the valid_count signal is active and resets to 0 when the reset signal ... | [
{
"content": "`timescale 1ns/1ps\nmodule counter_12_tb;\n\n reg clk, rst_n, valid_count;\n wire [3:0] out;\n\n counter_12 dut (\n .rst_n(rst_n),\n .clk(clk),\n .valid_count(valid_count),\n .out(out)\n );\n\n\n always #5 clk = ~clk;\n integer i = 0;\n integer error = 0;\n initial begin\n c... | `timescale 1ns/1ps
module counter_12
(
input rst_n,
input clk,
input valid_count,
output reg [3:0] out
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
begin
out <= 4'b0000;
end
else if (valid_count)
begin
if (out == 4'd11)
begin
out <= 4'b0000;... |
multi_pipe_8bit | Implement the design of unsigned 8bit multiplier based on pipelining processing. It utilizes a clock signal (clk), an active-low reset signal (rst_n), an input enable signal (mul_en_in), and provides an output enable signal (mul_en_out) and the product output (mul_out) of size 16 bits.
Module name:
multi_pipe_8b... | [
{
"content": "`timescale 1ns/1ns\n`define clk_period 20\nmodule tb_multi_pipe();\n \n reg [7:0] mul_a;\n reg [7:0] mul_b;\n reg mul_en_in;\n \n reg clk;\n reg rst_n;\n \n wire mul_en_out;\n wire [15:0] mul_out;\n\n reg [15:0] expected_product;\n \n multi_pipe_8bit u1(\n ... | module multi_pipe_8bit#(
parameter size = 8
)(
clk,
rst_n,
mul_a,
mul_b,
mul_en_in,
mul_en_out,
mul_out
);
input clk;
input rst_n;
input mul_en_in;
input [size-1:0] mul_a;
... |
radix2_div | Implement a simplified radix-2 divider on 8-bit signed or unsigned integers. and the inputs are two 8-bit operands. The module accepts a dividend and a divisor as inputs and provides a 16-bit result containing both the quotient and the remainder. The design supports both signed and unsigned division operations.
Module... | [
{
"content": "`timescale 1ns/1ps\n\nmodule radix2_div_tb;\n reg clk;\n reg rst;\n reg [7:0] dividend, divisor;\n reg sign;\n reg opn_valid;\n reg res_ready;\n wire res_valid;\n wire [15:0] result;\n\n // Instantiate the radix2_div module\n radix2_div uut (\n .clk(clk),\n ... | `timescale 1ns/1ps
module radix2_div(
input wire clk,
input wire rst,
input wire [7:0] dividend,
input wire [7:0] divisor,
input wire sign,
input wire opn_valid,
output reg res_valid,
input wire res_ready,
output wire [15:0] result
);
reg [7:0] dividend_... |
float_multi | Implement a module of a 32-bit floating-point multiplier for IEEE-754 standard single-precision arithmetic.
The float_multi module is designed to perform high-precision multiplication of 32-bit single-precision floating-point numbers, following the IEEE 754 standard. This module enables accurate arithmetic operations e... | [
{
"content": "module fmultiplier_tb;\n\nreg [31:0] a, b;\nwire [31:0] z;\nreg clk, rst;\n\nfloat_multi uut(clk , rst, a, b, z);\ninteger error = 0;\ninitial begin\n clk <= 0;\n rst <= 1;\n repeat(17000)\n #5 clk <= ~clk;\nend\n\ninitial #13 rst <= 0;\n\ninitial begin\n #3\n repeat(2) begin... | module float_multi(clk, rst, a, b, z);
input clk, rst;
input [31:0] a, b;
output reg [31:0] z;
reg [2:0] counter;
reg [23:0] a_mantissa, b_mantissa, z_mantissa; //Mantissa
reg [9:0] a_exponent, b_exponent, z_exponent; //EXPONENTS
reg a_sign, b_sign, z_sign; // Sign_Bit
reg [49:0] product;
reg guard_bit, round_bit,... |
instr_reg | An instruction register module designed to hold and process CPU instructions. It captures incoming instructions from various sources and separates them into distinct fields for further processing.
Module name:
instr_reg
Input ports:
clk: Clock signal for synchronization.
rst: Active low reset signal to in... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule instr_reg_tb;\n\nreg clk;\nreg rst;\nreg [1:0] fetch;\nreg [7:0] data;\n\nwire [2:0] ins;\nwire [4:0] ad1;\nwire [7:0] ad2;\n\ninstr_reg uut (\n .clk(clk),\n .rst(rst),\n .fetch(fetch),\n .data(data),\n .ins(ins),\n .ad1(ad1),\n .ad2(ad2)\n);\n\n... | module instr_reg (
input clk,
input rst,
input [1:0] fetch,
input [7:0] data,
output [2:0] ins,
output [4:0] ad1,
output [7:0] ad2
);
reg [7:0] ins_p1, ins_p2;
reg [2:0] state;
always @(posedge clk or negedge rst) begin
if (!rst) begin
ins_p1 <= 8'd0;
... |
accu | Implement a module to achieve serial input data accumulation output, input is 8bit data. The valid_in will be set to 1 before the first data comes in. Whenever the module receives 4 input data, the data_out outputs 4 received data accumulation results and sets the valid_out to be 1 (will last only 1 cycle).
Module nam... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule tb_valid_ready;\n\n\nparameter PERIOD = 10;\nreg clk = 0 ;\nreg rst_n = 0 ;\nreg [7:0] data_in = 0 ;\nreg valid_in = 0 ;\n\nwire valid_out ... | `timescale 1ns/1ns
module accu(
input clk ,
input rst_n ,
input [7:0] data_in ,
input valid_in ,
output reg valid_out ,
output reg [9:0] data_out
);
reg [1:0] count;
wire add_cnt;
wire rea... |
fsm | Implement a Mealy FSM detection circuit that detects a single-bit input IN. When the input is 10011, output MATCH is 1, and MATCH is 0 in other cases. Support for continuous input and loop detection.
Module name:
fsm
Input ports:
IN: Input signal to the FSM.
CLK: Clock signal used for syn... | [
{
"content": "`timescale 1ns/1ns\n\nmodule main();\n\nreg clk, rst;\nreg IN;\nwire MATCH;\n\nfsm DUT(.CLK(clk), .RST(rst), .IN(IN), .MATCH(MATCH));\n\ninitial begin\n clk = 0;\n forever #5 clk = ~clk;\nend\n\ninteger error = 0;\ninitial begin\n #10;\n rst = 1;\n #28;\n ... | module fsm(IN,MATCH,CLK,RST);
input IN,CLK,RST;
output reg MATCH;
reg [2:0] ST_cr,ST_nt;
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
parameter s5 = 3'b101;
always@(posedge CLK or posedge RST) begin
if(RST)
ST_cr <= s0;
else
... |
signal_generator | Implement a Triangle Wave signal generator module that generates a waveform by incrementing and decrementing a 5-bit signal named "wave". The waveform cycles between 0 and 31, which is incremented or decremented by 1.
Module name:
signal_generator
Input ports:
clk: Clock signal used for s... | [
{
"content": "module tb_signal_generator;\nreg clk,rst_n;\nwire[4:0] wave;\n\nsignal_generator uut(\n .clk(clk),\n .rst_n(rst_n),\n .wave(wave)\n );\n\nreg[31:0]reference[0:99];\n\ninteger i = 0;\ninteger error = 0;\n// integer ou... | module signal_generator(
input clk,
input rst_n,
output reg [4:0] wave
);
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= 2'b0;
wave <= 5'b0;
end
else begin
case (state)
2'b00:
begin
if (wave == 5'b11111)
... |
multi_8bit | Implement a module of an 8-bit multiplier based on shifting and adding operations.
Module name:
multi_8bit
Input ports:
A [7:0]: First 8-bit input operand (representing a multiplicand).
B [7:0]: Second 8-bit input operand (representing a multiplier).
Output ports:
product [15:0]: 16-bi... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n\n reg [7:0] A; // Input A (8 bits)\n reg [7:0] B; // Input B (8 bits)\n wire [15:0] product; // Product result (16 bits)\n integer i; // Loop variable\n integer error = 0; // Error count for failed tests\n\n multi_8... | module multi_8bit (
input [7:0] A,
input [7:0] B,
output reg [15:0] product
);
reg [7:0] multiplicand;
reg [3:0] shift_count;
always @* begin
product = 16'b0;
multiplicand = A;
shift_count = 0;
for (int i = 0; i < 8; i = i + 1) begin
if (B[i] == 1) begin
product = produc... |
freq_divbyeven | Frequency divider that divides the input clock frequency by even numbers. This module generates a divided clock signal by toggling its output every specified number of input clock cycles.
Module name:
freq_divbyeven
Input ports:
clk: Input clock signal that will be divided.
rst_n: Active-low reset signal... | [
{
"content": "`timescale 1ns / 1ps\nmodule testb_div_even;\n // Inputs\n reg clk;\n reg rst_n;\n // Outputs\n wire clk_div;\n \n // Instantiate the Unit Under Test (UUT)\n freq_divbyeven uut (\n .clk(clk), \n .rst_n(rst_n), \n .clk_div(clk_div)\n );\n always #5 cl... | module freq_divbyeven(
clk,
rst_n,
clk_div
);
input clk;
input rst_n;
output clk_div;
reg clk_div;
parameter NUM_DIV = 6;
reg [3:0] cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
cnt <= 4'd0;
clk_div <= 1'b0;
end
else if(cnt < NUM... |
adder_pipe_64bit | Implement a module of a 64-bit ripple carry adder, which includes several registers to enable the pipeline stages. The output result is available on the result port, and the o_en = 1 indicates the availability of the result.
Module name:
adder_pipe_64bit
Input ports:
clk: Clock input
rst_n... | [
{
"content": "module tb_adder64();\n\n parameter DATA_WIDTH = 64;\n parameter STG_WIDTH = 16;\n\n reg CLK;\n reg RST;\n reg i_en;\n wire o_en;\n reg [DATA_WIDTH-1:0] PLUS_A;\n reg [DATA_WIDTH-1:0] PLUS_B;\n wire [DATA_WIDTH:0] SUM_OUT;\n wire [DATA_WIDTH:0] sum_out_golden;\n reg [DATA_WIDTH:0] sum_ou... | module adder_pipe_64bit
#(
parameter DATA_WIDTH = 64,
parameter STG_WIDTH = 16
)
(
input clk,
input rst_n,
input i_en,
input [DATA_WIDTH-1:0] adda,
input [DATA_WIDTH-1:0] addb,
output [DATA_WIDTH:0] result,
output reg o_en
);
reg stage1;
reg stage2;
reg stage3;
wire [STG_WIDTH-1:0]... |
square_wave | The module is a simple yet effective generator designed to produce square wave signals with variable frequency. It takes an input clock signal and a frequency value, and outputs a square wave signal toggling at the specified frequency.
Module name:
square_wave
Input ports:
clk: Clock signa... | [
{
"content": "module square_wave_tb;\n\n reg clk_tb = 0; \n reg [8:0] freq_tb = 8'b0000100; \n wire wave_out_tb; \n integer ones_count = 0; // Counter for consecutive ones\n integer error = 0; // Error flag\n\n square_wave square_wave_inst (\n .clk(clk_tb),\n ... | module square_wave(
input clk,
input [7:0] freq,
output reg wave_out
);
reg [7:0] count;
initial begin
wave_out = 0;
count = 0;
end
always @(posedge clk) begin
if(count == freq - 1 ) begin
count <= 0;
wave_... |
div_16bit | Implement a 16-bit divider module, the dividend is 16-bit and the divider is 8-bit in combinational logic. Extract the higher bits of the dividend, matching the bit width of the divisor. Compare these bits with the divisor: if the dividend bits are greater, set the quotient to 1, otherwise set it to 0, and use the diff... | [
{
"content": "`timescale 1ns/1ps\nmodule tb_division();\n\nreg [15:0] A;\nreg [7:0] B;\nwire [15:0] result;\nwire [15:0] odd;\n\ninteger i; \ninteger error = 0; \nreg [15:0] expected_result;\nreg [15:0] expected_odd;\ninitial begin\n for (i = 0; i < 100; i = i + 1) begin\n A = $urandom_range(1'b0, 16'b11... | module div_16bit(
input wire [15:0] A,
input wire [7:0] B,
output wire [15:0] result,
output wire [15:0] odd
);
reg [15:0] a_reg;
reg [15:0] b_reg;
reg [31:0] tmp_a;
reg [31:0] tmp_b;
integer i;
always@(*) begin
a_reg = A;
b_reg = B;
end
always@(*) begin
begin
tmp_a = {16'b0, ... |
LIFObuffer | A Last-In-First-Out (LIFO) buffer for temporary data storage. This 4-bit wide buffer can hold up to 4 entries, allowing for push and pop operations controlled by read/write (RW) signals.
Module name:
LIFObuffer
Input ports:
dataIn [3:0]: 4-bit input data to be pushed onto the buffer.
RW: Read/Write contro... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule LIFObuffer_tb;\n\n// Inputs\nreg [3:0] dataIn;\nreg RW;\nreg EN;\nreg Rst;\nreg Clk;\n\n// Outputs\nwire [3:0] dataOut;\nwire EMPTY;\nwire FULL;\n\n// Instantiate the Unit Under Test (UUT)\nLIFObuffer uut (\n .dataIn(dataIn),\n .dataOut(dataOut),\n .RW(RW),\... | module LIFObuffer (
input [3:0] dataIn,
input RW,
input EN,
input Rst,
input Clk,
output reg EMPTY,
output reg FULL,
output reg [3:0] dataOut
);
reg [3:0] stack_mem[0:3];
reg [2:0] SP;
integer i;
always @ (posedge Clk) begin
if (EN == 0) begin
// Do ... |
multi_pipe_4bit | Implement the design of 4bit unsigned number pipeline multiplier. It consists of two levels of registers to store intermediate values and control the multiplication process.
Module name:
multi_pipe_4bit
Module parameter:
size = 4
Input ports:
clk: Clock signal used for synchronous operation.
rst_n... | [
{
"content": "`timescale 1ns/1ns\n\nmodule multi_pipe_tb;\n reg clk;\n reg rst_n;\n reg [3:0] mul_a;\n reg [3:0] mul_b;\n wire [7:0] mul_out;\n wire signed [7:0] perfect = mul_a*mul_b;\n // Instantiate the DUT (Design Under Test)\n multi_pipe_4bit #(.size(4)) dut (\n .clk(clk),\n .rst_n(rst_n),\n ... | `timescale 1ns/1ns
module multi_pipe_4bit#(
parameter size = 4
)(
input clk ,
input rst_n ,
input [size-1:0] mul_a ,
input [size-1:0] mul_b ,
output reg [size*2-1:0] mul_out ... |
right_shifter | Implement a right shifter. The module performs an 8-bit right shift on a 1-bit input by first initializing the q register to 0. On each rising edge of the clock, the module shifts the contents of the q register to the right by one bit and inserts the new input bit d into the most significant position of the register.
... | [
{
"content": "`timescale 1ns/1ns\nmodule right_shifter_tb;\n reg clk;\n reg d;\n wire [7:0] q;\n\n // Instantiate the DUT (Design Under Test)\n right_shifter dut (\n .clk(clk),\n .d(d),\n .q(q)\n );\n\n // Generate clock\n always #5 clk = ~clk;\n\n initial begin\n // Initialize inputs\n ... | module right_shifter(clk, q,d);
input clk;
input d;
output [7:0] q;
reg [7:0] q;
initial q = 0;
always @(posedge clk)
begin
q <= (q >> 1);
q[7] <= d;
end
endmodule |
freq_divbyodd | A frequency divider that divides the input clock frequency by odd numbers. The module generates a divided clock output by an odd divisor value provided as a parameter.
Module name:
freq_divbyodd
Input ports:
clk: Input clock signal.
rst_n: Active low reset signal that initializes the divider.
Output ... | [
{
"content": "`timescale 1ns / 1ps\nmodule testb_div_odd;\n // Inputs\n reg clk;\n reg rst_n;\n // Outputs\n wire clk_div;\n \n // Instantiate the Unit Under Test (UUT)\n freq_divbyodd uut (\n .clk(clk), \n .rst_n(rst_n), \n .clk_div(clk_div)\n );\n always #5 clk ... | module freq_divbyodd(
clk,
rst_n,
clk_div
);
input clk;
input rst_n;
output clk_div;
reg clk_div;
parameter NUM_DIV = 5;
reg[2:0] cnt1;
reg[2:0] cnt2;
reg clk_div1, clk_div2;
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt1 <= 0;
else if(cnt1 < NUM_... |
barrel_shifter | Module name:
barrel_shifter
Function:
A barrel shifter for rotating bits efficiently. This 8-bit barrel shifter takes an 8-bit input and shifts or rotates the bits based on a 3-bit control signal.
Input ports:
in [7:0]: 8-bit input to be shifted.
ctrl [2:0]: 3-bit control signal that determines how m... | [
{
"content": "module barrel_shifter_tb;\n reg [7:0] in;\n reg [2:0] ctrl;\n wire [7:0] out; \n \nbarrel_shifter uut(.in(in), .ctrl(ctrl), .out(out));\n\ninteger error = 0;\n\ninitial \n begin\n in= 8'd0; ctrl=3'd0; //no shift\n #10 in=8'd128; ctrl= 3'd4; //shift 4 bit\n #10 error = ... | module barrel_shifter (in, ctrl, out);
input [7:0] in;
input [2:0] ctrl;
output [7:0] out;
wire [7:0] x,y;
//4bit shift right
mux2X1 ins_17 (.in0(in[7]),.in1(1'b0),.sel(ctrl[2]),.out(x[7]));
mux2X1 ins_16 (.in0(in[6]),.in1(1'b0),.sel(ctrl[2]),.out(x[6]));
mux2X1 ins_15 (.in0(in[5]),.in1(1'b0),.sel(ctrl[2]... |
comparator_3bit | Implement a module of a 3-bit comparator for comparing binary numbers.
Module name:
comparator_3bit
Input ports:
A [2:0]: First 3-bit input operand (the first binary number to compare).
B [2:0]: Second 3-bit input operand (the second binary number to compare).
Output ports:
A_greater: ... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n\n reg [2:0] A; // Input A (3 bits)\n reg [2:0] B; // Input B (3 bits)\n wire A_greater; \n wire A_equal; \n wire A_less; \n integer i; \n integer error = 0; \n\n comparator_3bit uut (\n .A... | module comparator_3bit (
input [2:0] A,
input [2:0] B,
output A_greater,
output A_equal,
output A_less
);
assign A_greater = (A > B) ? 1'b1 : 1'b0;
assign A_equal = (A == B) ? 1'b1 : 1'b0;
assign A_less = (A < B) ? 1'b1 : 1'b0;
endmodule |
adder_32bit | Implement a module of a carry-lookahead 32-bit adder that uses the Carry-Lookahead Adder (CLA) architecture.
Module name:
adder_32bit
Input ports:
A[32:1]: 32-bit input operand A.
B[32:1]: 32-bit input operand B.
Output ports:
S[32:1]: 32-bit output representing the sum of A and B.
... | [
{
"content": "`timescale 1ns/1ns\nmodule adder32_tb;\n \n reg [31:0] A;\n reg [31:0] B;\n wire [31:0] S;\n wire C32;\n \n integer i; \n integer error = 0; \n reg [33:0] expected_sum; \n \n // Instantiate the module\n adder_32bit uut (\n .A(A), \n .B(B), \n .S(S), \n .C32(C32)\n );\n \... | module adder_32bit(A,B,S,C32);
input [32:1] A;
input [32:1] B;
output [32:1] S;
output C32;
wire px1,gx1,px2,gx2;
wire c16;
CLA_16 CLA1(
.A(A[16:1]),
.B(B[16:1]),
.c0(0),
.S(S[16:1]),
.px(px1),
.gx(gx1)
);
CLA_16 CLA2(
.A(A[3... |
adder_bcd | Implement a module of a 4-bit BCD adder for decimal arithmetic operations.
Module name:
adder_bcd
Input ports:
A [3:0]: First BCD input (4-bit, representing a decimal digit from 0 to 9).
B [3:0]: Second BCD input (4-bit, representing a decimal digit from 0 to 9).
Cin: Carry-in input (... | [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n\n reg [3:0] A; // First BCD input (4 bits)\n reg [3:0] B; // Second BCD input (4 bits)\n reg Cin; // Carry-in input (1 bit)\n wire [3:0] Sum; // BCD sum output (4 bits)\n wire Cout; // Carry-out output (1 bit)\n\n integer i; ... | module adder_bcd (
input [3:0] A, // First BCD number (0-9)
input [3:0] B, // Second BCD number (0-9)
input Cin, // Input carry
output [3:0] Sum, // BCD sum (0-9)
output Cout // Output carry
);
wire [4:0] temp_sum; // Temporary 5-bit sum to store initial result
wire... |
synchronizer | Implement a multi-bit MUX-based synchronizer, data_in will remain constant during the period when data_en is high, and data_en is high for at least 3 clk_b clock cycles. When the value of data_en is high, data can be synchronized. The data change frequency of data_in is very low. The change interval between two adjacen... | [
{
"content": "`timescale 1ns/1ns\n\nmodule testbench;\n // Inputs\n reg clk_a;\n reg clk_b;\n reg arstn;\n reg brstn;\n reg [3:0] data_in;\n reg data_en;\n\n // Outputs\n wire [3:0] dataout;\n\n // Instantiate the mux module\n synchronizer dut(\n .clk_a(clk_a),\n .... | module synchronizer(
input clk_a ,
input clk_b ,
input arstn ,
input brstn ,
input [3:0] data_in ,
input data_en ,
output reg [3:0] dataout
);
reg [3:0] data_reg;
always@(pos... |
End of preview. Expand in Data Studio
RTLLM V2.0
Huggingface Datasets format of RTLLM 2.0.
I'm not the author of this work; please refer to original repository to get more info.
Columns:
desc: Design description;testbench: All testbench-related files, includingtestbench.v,makefile, etc.;name: File name;content: File content;
verified: Verified implementation; Theverified_prefix is removed.
Example usage:
dataset = datasets.load_dataset("observerw/RTLLM", split="test")
for item in dataset:
with tempfile.TemporaryDirectory() as tempdir:
generation = LLM.generate(item["desc"])
(Path(tempdir) / "impl.v").write_text(generation)
for tb in item["testbench"]: # write all testbench-related files into temp dir
(Path(tempdir) / tb["name"]).write_text(tb["content"])
subprocess.run(["make"], cwd=tempdir)
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