id stringlengths 2 23 | prompt stringlengths 512 5.35k | spec_changed bool 2 classes | tb_changed bool 1 class | golden_changed bool 2 classes | base_module_name stringlengths 3 25 | mod_module_name stringlengths 2 22 | semantic_tags listlengths 1 5 |
|---|---|---|---|---|---|---|---|
JC_counter | Please act as a professional verilog designer.
Implement a 64-bit Johnson counter (torsional ring counter), and the state of the similar 4-bit Johnson counter example is as follows: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000.
Module name:
JC_counter
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal to initialize the counter.
Output port:
Q: 64-bit register representing the current count value.
Implementation:
On every rising edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the counter value is updated.
If the reset signal (rst_n) is low, indicating a reset condition, the counter value (Q) is set to 0.
Otherwise, if the least significant bit (Q[0]) is 0, the counter increments by shifting the current value (Q[63:1]) to the right and appending a 1 at the most significant bit position.
If the least significant bit (Q[0]) is 1, the counter decrements by shifting the current value (Q[63:1]) to the right and appending a 0 at the most significant bit position.
Give me the complete code. | false | true | true | verified_JC_counter | JC_counter | [
"module_name_alignment",
"testbench_output_standardization"
] |
LFSR | Please act as a professional Verilog designer.
A Linear Feedback Shift Register (LFSR) designed for generating pseudo-random sequences. This 4-bit LFSR uses a specific feedback mechanism to produce a sequence of bits that appears random.
Module name:
LFSR
Input ports:
clk: Clock signal to synchronize the shifting operation.
rst: Active high reset signal to initialize the register.
Output ports:
out [3:0]: 4-bit output representing the current state of the LFSR.
Implementation:
The LFSR operates on the principle of shifting bits and applying feedback based on the XOR of specific bits in the register.
The feedback is calculated by XORing the most significant bit (out[3]) and the second most significant bit (out[2]). The result is inverted to produce the feedback signal.
On the rising edge of the clock (clk), if the reset (rst) is high, the register is initialized to zero. Otherwise, the bits in the register are shifted left, and the new feedback value is inserted at the least significant bit (LSB). | false | true | false | LFSR | LFSR | [
"testbench_output_standardization"
] |
LIFObuffer | Please act as a professional Verilog designer.
A Last-In-First-Out (LIFO) buffer for temporary data storage. This 4-bit wide buffer can hold up to 4 entries, allowing for push and pop operations controlled by read/write (RW) signals.
Module name:
LIFObuffer
Input ports:
dataIn [3:0]: 4-bit input data to be pushed onto the buffer.
RW: Read/Write control signal (1 for read, 0 for write).
EN: Enable signal to activate buffer operations.
Rst: Active high reset signal to initialize the buffer.
clk: Clock signal for synchronous operations.
Output ports:
EMPTY: Flag indicating whether the buffer is empty.
FULL: Flag indicating whether the buffer is full.
dataOut [3:0]: 4-bit output data retrieved from the buffer.
Implementation:
The buffer uses a stack memory array (stack_mem) to store the data. A stack pointer (SP) tracks the current position in the stack.
On the rising edge of the clock (clk), if the enable (EN) signal is high:
If the reset (Rst) signal is high, the stack is cleared, the stack pointer is set to 4 (indicating an empty buffer), and all memory locations are initialized to 0.
If the reset signal is low, the buffer checks if it is full or empty and processes data accordingly:
If RW is low (write operation) and the buffer is not full, data from dataIn is pushed onto the stack, and the stack pointer is decremented.
If RW is high (read operation) and the buffer is not empty, data is popped from the stack into dataOut, the corresponding stack memory is cleared, and the stack pointer is incremented.
Flags for EMPTY and FULL are updated based on the stack pointer status.
Give me the complete code. | true | true | true | LIFObuffer | LIFObuffer | [
"golden_signal_name_normalization",
"spec_case_normalization",
"testbench_output_standardization"
] |
RAM | Please act as a professional verilog designer.
Implement a dual-port RAM with a depth of 8 and a bit width of 6 bits, with all data initialized to 000000. It has two groups of ports, respectively for reading data and writing data, and read and write operations can be carried out at the same time. When the read_en signal is 1, the read_data of the corresponding position is read through the read_addr signal and output; When the write_en signal is 1, data is written to the corresponding position through the write_addr signal and write-data signal.
Module name:
RAM
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for reset and 1 for reset signal inactive.
write_en: Write enable signal to initiate a write operation.
write_addr: Address for the write operation.
write_data: Data to be written to the RAM.
read_en: Read enable signal to initiate a read operation.
read_addr: Address for the read operation.
Output ports:
read_data: Output signal representing the data read from the RAM.
Parameter:
WIDTH = 6;
DEPTH = 8;
Implementation:
RAM Array:
The module includes a register array, RAM. The array is defined as reg [DEPTH - 1 : 0] RAM [2**WIDTH-1:0], allowing for 2^6 memory locations, each with a width of 6 bits.
Write Operation:
The first always block triggers on the positive edge of the clock signal (posedge clk) or the negative edge of the reset signal (negedge rst_n).
On reset, indicated by !rst_n, all memory locations in the RAM array are cleared to 0.
If the write enable signal (write_en) is active, the data (write_data) is written to the RAM array at the specified address (write_addr).
Read Operation:
The second always block triggers on the positive edge of the clock signal (posedge clk) or the negative edge of the reset signal (negedge rst_n).
On reset, indicated by !rst_n, the read_data register is cleared to 0.
If the read enable signal (read_en) is active, the data at the specified address (read_addr) in the RAM array is assigned to the read_data register.
If the read enable signal is not active, the read_data register is cleared to 0.
Give me the complete code. | false | true | true | verified_RAM | RAM | [
"module_name_alignment",
"testbench_output_standardization"
] |
ROM | Please act as a professional Verilog designer.
A Read-Only Memory (ROM) module designed for storing fixed data. This module provides a way to access predefined data based on an 8-bit address input.
Module name:
ROM
Input ports:
addr [7:0]: 8-bit address input used to select the data location in memory.
Output ports:
dout [15:0]: 16-bit output that delivers the data stored in the ROM at the specified address.
Memory Array:
reg [15:0] mem [0:255]: Defines a ROM with 256 locations, each 16 bits wide.
Initial Block:
The initial block is used to pre-load the ROM with fixed data. In this example, memory locations 0 through 3 are initialized with specific values (16'hA0A0, 16'hB1B1, 16'hC2C2, 16'hD3D3). Other locations can be initialized as needed.
Behavior:
The always @(*) block continuously outputs the data stored in the ROM at the memory location specified by addr.
Since ROM is read-only, this module includes only read operations.
Give me the complete code. | false | true | false | ROM | ROM | [
"testbench_output_standardization"
] |
accu | Please act as a professional verilog designer.
Implement a module to achieve serial input data accumulation output, input is 8bit data. The valid_in will be set to 1 before the first data comes in. Whenever the module receives 4 input data, the data_out outputs 4 received data accumulation results and sets the valid_out to be 1 (will last only 1 cycle).
Module name:
accu
Input ports:
clk: Clock input for synchronization.
rst_n: Active-low reset signal.
data_in[7:0]: 8-bit input data for addition.
valid_in: Input signal indicating readiness for new data.
Output ports:
valid_out: Output signal indicating when 4 input data accumulation is reached.
data_out[9:0]: 10-bit output data representing the accumulated sum.
Implementation:
When valid_in is 1, data_in is a valid input. Accumulate four valid input data_in values and calculate the output data_out by adding these four values together.
There is no output when there are fewer than four data_in inputs in the interim. Along with the output data_out, a cycle of valid_out=1 will appear as a signal.
The valid_out signal is set to 1 when the data_out outputs 4 received data accumulation results. Otherwise, it is set to 0.
Give me the complete code. | false | true | true | verified_accu | accu | [
"module_name_alignment",
"testbench_output_standardization"
] |
adder_16bit | Please act as a professional verilog designer.
Implement a module of a 16-bit full adder in combinational logic.
Module name:
adder_16bit
Input ports:
a[15:0]: 16-bit input operand A.
b[15:0]: 16-bit input operand B.
Cin: Carry-in input.
Output ports:
y[15:0]: 16-bit output representing the sum of A and B.
Co: Carry-out output.
Implementation:
In the adder_16bit module, you need to design a small bit-width adder(8-bit adder), which will be instantiated multiple times.
Give me the complete code. | false | true | true | verified_adder_16bit | adder_16bit | [
"module_name_alignment",
"testbench_output_standardization"
] |
adder_32bit | Please act as a professional verilog designer.
Implement a module of a carry-lookahead 32-bit adder that uses the Carry-Lookahead Adder (CLA) architecture.
Module name:
adder_32bit
Input ports:
A[32:1]: 32-bit input operand A.
B[32:1]: 32-bit input operand B.
Output ports:
S[32:1]: 32-bit output representing the sum of A and B.
C32: Carry-out output.
Implementation:
The top module adder_32bit consists of several instances of the 16 bit CLA block you design.
Give me the complete code. | false | true | true | verified_adder_32bit | adder_32bit | [
"module_name_alignment",
"testbench_output_standardization"
] |
adder_8bit | Please act as a professional verilog designer.
Implement a module of an 8-bit adder with multiple bit-level adders in combinational logic.
Module name:
adder_8bit
Input ports:
a[7:0]: 8-bit input operand A.
b[7:0]: 8-bit input operand B.
cin: Carry-in input.
Output ports:
sum[7:0]: 8-bit output representing the sum of A and B.
cout: Carry-out output.
Implementation:
The module utilizes a series of bit-level adders (full adders) to perform the addition operation.
Give me the complete code. | false | true | true | verified_adder_8bit | adder_8bit | [
"module_name_alignment",
"testbench_output_standardization"
] |
adder_bcd | Please act as a professional verilog designer.
Implement a module of a 4-bit BCD adder for decimal arithmetic operations.
Module name:
adder_bcd
Input ports:
A [3:0]: First BCD input (4-bit, representing a decimal digit from 0 to 9).
B [3:0]: Second BCD input (4-bit, representing a decimal digit from 0 to 9).
Cin: Carry-in input (1-bit).
Output ports:
Sum [3:0]: 4-bit output representing the sum of the two BCD inputs, corrected to be a valid BCD digit (0–9).
Cout: Carry-out output (1-bit), used when the sum exceeds the decimal value of 9.
Implementation:
Addition: The module performs binary addition of A, B, and Cin.
BCD Correction: If the sum exceeds 9 (binary 1001), a correction of 6 (binary 0110) is added to the sum. This correction ensures that the result is within the BCD range.
Carry Generation: If the result of the addition exceeds 9, a carry-out (Cout) is generated, signaling that the BCD sum exceeds a single decimal digit.
Give me the complete code. | false | true | false | adder_bcd | adder_bcd | [
"testbench_output_standardization"
] |
adder_pipe_64bit | Please act as a professional verilog designer.
Implement a module of a 64-bit ripple carry adder, which includes several registers to enable the pipeline stages. The output result is available on the result port, and the o_en = 1 indicates the availability of the result.
Module name:
adder_pipe_64bit
Input ports:
clk: Clock input
rst_n: Active low reset signal
i_en: Enable signal for addition operation
adda: 64-bit input operand A
addb: 64-bit input operand B
Output ports:
result: 65-bit output representing the sum of adda and addb.
o_en: Output enable signal.
Implementation:
The module includes several registers to enable the pipeline stages and synchronize the input enable signal (i_en). These registers are controlled by the clock (clk) and reset (rst_n) signals.
The sum values for each pipeline stage are calculated by adding the corresponding input operands and carry signals.
The output enable signal (o_en) is updated based on the pipeline stages and synchronized with the clock (clk) and reset (rst_n) signals.
Give me the complete code. | false | true | true | verified_adder_64bit | adder_pipe_64bit | [
"module_name_alignment",
"testbench_output_standardization"
] |
alu | Please act as a professional verilog designer.
Implement an ALU for a 32-bit MIPS-ISA CPU. The “a” and “b” are the two operands of the ALU, the “aluc” is the opcode, and the “r” gives out the result. “zero” means if the result is zero, “carry” means if there is a carry bit, “negative” means if the result is negative, “overflow” means if the computation is overflow, the “flag” is the result of “slt” and “sltu” instructions. The supported operations and corresponding opcode are shown below:
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter LUI = 6'b001111;
Module name:
alu
Input ports:
a: a 32-bit input operand
b: a 32-bit input operand
aluc: a 6-bit control signal for selecting the operation to be performed
Output ports:
r: a 32-bit output representing the result of the operation
zero: a 1-bit output indicating whether the result is zero
carry: a 1-bit output indicating whether a carry occurred during the operation
negative: a 1-bit output indicating whether the result is negative
overflow: a 1-bit output indicating whether an overflow occurred during the operation
flag: a 1-bit output representing a general flag, which is set based on specific operations (SLT and SLTU)
Implementation:
The module uses parameters to define the control signals for various operations, such as ADD, SUB, AND, OR, etc.
The module assigns the input operands to the signed wires and the output result (r) to the lower 32 bits of the register (res[31:0]). The flag output is determined based on the control signal (aluc) and is set to '1' when the operation is SLT or SLTU, and 'z' (high-impedance) otherwise. The zero output is set to '1' when the result is all zeros, and '0' otherwise.
Inside the always block, a case statement is used to perform the appropriate operation based on the control signal (aluc). The result is assigned to the register (res) accordingly. For shift operations (SLL, SRL, SRA, SLLV, SRLV, SRAV), the shift amount is determined by the value of 'a' or 'a[4:0]'. For the LUI operation, the upper 16 bits of 'a' are concatenated with 16 zeros to form the result.
If the control signal (aluc) does not match any defined operation, the result is assigned as 'z' (high-impedance).
Give me the complete code. | false | true | true | verified_alu | alu | [
"module_name_alignment",
"testbench_output_standardization"
] |
asyn_fifo | Please act as a professional verilog designer.
Implement an asynchronous FIFO, FIFO bit width and depth can be configured(parameter DEPTH = 16, parameter WIDTH = 8). The asynchronous FIFO structure is divided into several parts. The first part is dual-port RAM, which is used for data storage. Instantiate dual-port RAM as a submodule, The RAM ports are input clk, input wenc, input [$clog2(DEPTH)-1:0] waddr, input [WIDTH-1:0] wdata, input rclk, input renc, input [$clog2(DEPTH)-1:0] raddr, output reg [WIDTH-1:0] rdata. The second part is the data write controller. The third part is the data read controller. The fourth part is the read pointer synchronizer. The read pointer is collected using the two-stage trigger of the write clock and output to the data write controller. The fifth part is the write pointer synchronizer, which uses the two-stage trigger of the read clock to collect the write pointer and output it to the data read controller.
The method of empty and full judgment is to generate empty and full signals by comparing the Gray code. Use 4-bit Gray code as a read/write pointer for a FIFO with depth 8. The gray code is converted to a four-digit binary number, using the lower three digits of the binary number as the address to access RAM. When the read and write Pointers are equal, the FIFO is null.
When the write pointer has one more cycle RAM than the read pointer, the highest and second-highest bits of the read and write pointer are opposite, the remaining bits are the same, and the FIFO is full.
Module name:
asyn_fifo
Input ports:
clk: Write clock signal used for synchronous write operations.
rclk: Read clock signal used for synchronous read operations.
wrstn: Write reset signal. Defined as 0 for reset and 1 for reset signal inactive.
rrstn: Read reset signal. Defined as 0 for reset and 1 for reset signal inactive.
winc: Write increment signal. Used to trigger write operations.
rinc: Read increment signal. Used to trigger read operations.
wdata: Write data input. The width [WIDTH-1:0] is configurable and represents the data to be written into the FIFO.
Output ports:
wfull: Write full signal. Indicates if the FIFO is full and cannot accept further write operations.
rempty: Read empty signal. Indicates if the FIFO is empty and cannot provide any data for read operations.
rdata: Read data output. The width [WIDTH-1:0] is configurable and represents the data read from the FIFO.
Parameter:
WIDTH = 8
DEPTH = 16
Implementation:
The module implements an asynchronous FIFO using a dual-port RAM module and additional logic for managing read and write pointers.
Dual-port RAM:
The module instantiates a dual-port RAM module named "dual_port_RAM" with configurable depth and width.
The RAM module has separate clock inputs for write (clk) and read (rclk) operations.
The RAM module has separate address inputs for write (waddr) and read (raddr) operations.
The RAM module has a write enable input (wenc) and a write data input (wdata).
The RAM module has a read enable input (renc) and a read data output (rdata).
The RAM module stores data in a two-dimensional array, RAM_MEM, with a size of DEPTH by WIDTH.
Write and Read Pointers:
The module includes logic to manage write and read pointers for asynchronous operation.
The write and read pointers are represented by binary registers, waddr_bin and raddr_bin, respectively.
The write and read pointers are incremented based on the write and read increment signals (winc and rinc), respectively.
The write pointer is incremented on the positive edge of the write clock (posedge clk) and reset to 0 on write reset (~wrstn).
The read pointer is incremented on the positive edge of the read clock (posedge rclk) and reset to 0 on read reset (~rrstn).
Gray Code Conversion:
The write and read pointers are converted to Gray code using XOR operations with right-shifted values.
The converted write and read pointers are stored in registers wptr and rptr, respectively.
The Gray code conversion reduces glitches and ensures proper synchronization of the write and read pointers.
Pointer Buffers:
The module includes buffer registers (wptr_buff and rptr_buff) to hold the previous values of the write and read pointers.
The buffer registers are updated on the positive edge of the respective clocks and reset to 0 on the respective resets (~wrstn and ~rrstn).
The buffer registers are used to synchronize the write and read pointers for determining the full and empty conditions.
Full and Empty Signals:
The module compares the current write and read pointers (wptr and rptr_syn) to determine if the FIFO is full or empty.
The wfull output is set to 1 when the write pointer is equal to the bitwise negation of the most significant bit of the read pointer concatenated with the remaining bits of the read pointer.
The rempty output is set to 1 when the read pointer is equal to the write pointer.
Input and Output Connections:
The module connects the input and output signals to the dual-port RAM module based on the control signals and pointer values.
The wen and ren signals control the write and read enable signals of the RAM module, respectively.
The wdata input is connected to the write data input (wdata) of the RAM module.
The rdata output is connected to the read data output (rdata) of the RAM module.
Give me the complete code. | true | true | true | dual_port_RAM | dual_port_RAM | [
"golden_signal_name_normalization",
"known_wclk_to_clk_unification",
"spec_signal_name_normalization",
"testbench_output_standardization"
] |
barrel_shifter | Please act as a professional verilog designer.
Module name:
barrel_shifter
Function:
A barrel shifter for rotating bits efficiently. This 8-bit barrel shifter takes an 8-bit input and shifts or rotates the bits based on a 3-bit control signal.
Input ports:
in [7:0]: 8-bit input to be shifted.
ctrl [2:0]: 3-bit control signal that determines how many positions to shift. The control signal specifies the amount of shift, where each bit indicates a shift by 1, 2, or 4 positions.
Output ports:
out [7:0]: 8-bit shifted output.
Implementation:
The barrel shifter shifts the input `in` based on the value of the `ctrl` signal. The shifting happens in stages, where each stage shifts by 4, 2, or 1 position, as controlled by `ctrl[2]`, `ctrl[1]`, and `ctrl[0]`, respectively.
The shifts are achieved using a series of 2-to-1 multiplexers (`mux2X1`) that select between the shifted input and the original input. Each stage of multiplexers performs the shift, and the result is passed to the next stage for further shifting if required.
- When `ctrl[2]` is high, the input is shifted by 4 positions.
- When `ctrl[1]` is high, the intermediate result is shifted by 2 positions.
- When `ctrl[0]` is high, the intermediate result is shifted by 1 position.
The `mux2X1` submodule is used to select between two input values based on the `sel` signal, determining which bit is used in the shifted output at each stage.
Give me the complete code. | false | true | false | barrel_shifter | barrel_shifter | [
"testbench_output_standardization"
] |
calendar | Please act as a professional verilog designer.
Implement a module of perpetual calendar. The starting value of Secs, Mins, and Hours are all 0. Both Secs and Mins loop continuously from 0 to 59. When Secs=59, Min increases by 1 at the next cycle, and when Min=59 && Secs=59, Hours increases by 1 at the next cycle. Hours is counted from the 0-23 cycle.
Module name:
calendar
Input ports:
clk: Clock input
RST: Active high reset signal
Output ports:
Hours: 6-bit output representing the current hours
Mins: 6-bit output representing the current minutes
Secs: 6-bit output representing the current seconds
Implementation:
The calendar module uses three always blocks to update the values of seconds, minutes, and hours based on the clock signal and reset signal.
The first always block triggers on the positive edge of the clock signal (posedge clk) or the positive edge of the reset signal (posedge RST). It checks if the reset signal is active (RST) and sets the seconds value (Secs) to 0. If the seconds value is 59, it wraps around and sets the seconds value to 0. Otherwise, it increments the seconds value by 1.
The second always block also triggers on the positive edge of the clock signal or the positive edge of the reset signal. It handles the minutes value (Mins). If the reset signal is active, it sets the minutes value to 0. If both the minutes and seconds values are 59, it wraps around and sets the minutes value to 0. If the seconds value is 59, it increments the minutes value by 1. Otherwise, it keeps the minutes value unchanged.
The third always block triggers on the positive edge of the clock signal or the positive edge of the reset signal. It handles the hours value (Hours). If the reset signal is active, it sets the hours value to 0. If the hours, minutes, and seconds values are all at their maximum (23, 59, and 59 respectively), it wraps around and sets the hours value to 0. If the minutes and seconds values are both 59, it increments the hours value by 1. Otherwise, it keeps the hours value unchanged.
Give me the complete code. | true | true | true | verified_calendar | calendar | [
"golden_signal_name_normalization",
"known_clk_case_unification",
"module_name_alignment",
"spec_case_normalization",
"testbench_output_standardization"
] |
clkgenerator | Please act as a professional Verilog designer.
A clock generator module that produces a periodic clock signal, toggling its output state at regular intervals defined by the PERIOD parameter.
Module name:
clkgenerator
Parameter:
PERIOD = 10
Output ports:
clk: The output clock signal generated by the module.
Implementation:
This module uses an initial block to set the initial state of the clock signal to 0. The clock toggles every half of the specified PERIOD, creating a square wave clock signal with the desired frequency.
Give me the complete code. | false | true | true | clkgenerator | clkgenerator | [
"testbench_output_standardization"
] |
comparator_3bit | Please act as a professional Verilog designer.
Implement a module of a 3-bit comparator for comparing binary numbers.
Module name:
comparator_3bit
Input ports:
A [2:0]: First 3-bit input operand (the first binary number to compare).
B [2:0]: Second 3-bit input operand (the second binary number to compare).
Output ports:
A_greater: 1-bit output indicating if A is greater than B.
A_equal: 1-bit output indicating if A is equal to B.
A_less: 1-bit output indicating if A is less than B.
Implementation:
Comparison Logic: The module compares the two 3-bit binary numbers A and B using combinational logic.
- The outputs A_greater, A_equal, and A_less are determined based on the comparison of A and B.
- A_greater is set to 1 if A > B, A_equal is set to 1 if A == B, and A_less is set to 1 if A < B.
Output Encoding: The outputs are mutually exclusive, meaning only one of the three outputs will be high (1) at any given time, based on the comparison results.
Give me the complete code. | false | true | false | comparator_3bit | comparator_3bit | [
"testbench_output_standardization"
] |
comparator_4bit | Please act as a professional Verilog designer.
Implement a module of a 4-bit comparator with multiple bit-level comparators in combinational logic.
Module name:
comparator_4bit
Input ports:
A [3:0]: First 4-bit input operand (binary number to compare).
B [3:0]: Second 4-bit input operand (binary number to compare).
Output ports:
A_greater: 1-bit output indicating if A is greater than B.
A_equal: 1-bit output indicating if A is equal to B.
A_less: 1-bit output indicating if A is less than B.
Implementation:
Comparison Logic: The module compares the two 4-bit binary numbers A and B using combinational logic.
- A subtraction operation is performed: A - B. The result of this subtraction helps determine whether A is greater than, equal to, or less than B.
- Carry Generation: If a borrow occurs during the subtraction, A is less than B (A_less).
- If no borrow occurs and the result of subtraction is non-zero, A is greater than B (A_greater).
- If A and B are equal, the result of subtraction is zero (A_equal).
Output Encoding: The outputs (A_greater, A_equal, A_less) are mutually exclusive, ensuring only one of the three outputs is high (1) at any given time.
Give me the complete code. | false | true | false | comparator_4bit | comparator_4bit | [
"testbench_output_standardization"
] |
counter_12 | Please act as a professional verilog designer.
Implement a module of a counter design that requires counting from 4 'b0000 to 4' d11. The counting can be controlled by the input signal valid_count. That is, the count is paused if valid_count is 0. The counter increments on each clock cycle when the valid_count signal is active and resets to 0 when the reset signal (rst_n) is active.
Module name:
counter_12
Input ports:
rst_n: Reset signal (active low)
clk: Clock signal
valid_count: Signal to enable counting
Output ports:
out: 4-bit output representing the current count value
Implementation:
If the reset signal is active (!rst_n), the counter is reset to 0 by assigning the value 4'b0000 to the output register (out). If the valid_count signal is 1, the counter increments. It checks if the current count value (out) is equal to 4'd11 (maximum count value). If it is, the counter wraps around and resets to 0 by assigning the value 4'b0000 to the output register (out). Otherwise, it increments the output register by 1. If the valid_count = 0, the counter will stop, and the output register (out) remains unchanged.
Give me the complete code. | false | true | true | verified_counter_12 | counter_12 | [
"module_name_alignment",
"testbench_output_standardization"
] |
div_16bit | Please act as a professional verilog designer.
Implement a 16-bit divider module, the dividend is 16-bit and the divider is 8-bit in combinational logic. Extract the higher bits of the dividend, matching the bit width of the divisor. Compare these bits with the divisor: if the dividend bits are greater, set the quotient to 1, otherwise set it to 0, and use the difference as the remainder. Concatenate the remainder with the highest remaining 1-bit of the dividend, and repeat the process until all dividend bits are processed.
Module name:
div_16bit
Input ports:
A: 16-bit dividend.
B: 8-bit divisor.
Output ports:
result: 16-bit quotient.
odd: 16-bit remainder.
Implementation:
The module uses two always blocks to perform the division operation.
The first always block is a combinational block triggered by any change in the input values A and B. It updates the values of two registers, a_reg and b_reg, with the values of A and B, respectively.
The second always block is also a combinational block triggered by any change in the input values A and B.
Give me the complete code. | false | true | true | verified_div_16bit | div_16bit | [
"module_name_alignment",
"testbench_output_standardization"
] |
edge_detect | Please act as a professional verilog designer.
Implement a module for edge detection. There is a slowly changing 1-bit signal a. When "a" changes from 0 to 1, the indicating signal rise is 1. When "a" changes from 1 to 0, the falling edge of signal a is shown, the indicating signal down is 1. rise or down will be set to 1 on the next clock when the corresponding edge appears, and then return to 0 until the corresponding edge appears again.
Module name:
edge_detect
Input ports:
clk: Clock signal.
rst_n: Reset signal (active low).
a: Input signal.
Output ports:
rise: Output signal indicating a rising edge.
down: Output signal indicating a falling edge.
Implementation:
The edge_detect module detects rising and falling edges in the input signal a and generates corresponding output signals rise and down. The rising and falling edges are detected on the positive edge of the clock signal clk. If a rising edge is detected, the rise output signal is set to 1. If a falling edge is detected, the down output signal is set to 1. Otherwise, both output signals are set to 0. These output signals are synchronized with the clock and remain set to 1 until the corresponding edge appears again.
Give me the complete code. | false | true | true | verified_edge_detect | edge_detect | [
"module_name_alignment",
"testbench_output_standardization"
] |
fixed_point_adder | Please act as a professional Verilog designer.
Implement a module of a parameterized fixed-point adder for arithmetic operations with fixed precision.
Module name:
fixed_point_adder
Input parameters:
Q: Number of fractional bits (precision).
N: Total number of bits, including integer and fractional parts.
Input ports:
a [N-1:0]: First N-bit fixed-point input operand.
b [N-1:0]: Second N-bit fixed-point input operand.
Output ports:
c [N-1:0]: N-bit output representing the result of the fixed-point addition.
Internal Registers:
res [N-1:0]: N-bit register used to store the result of the addition or subtraction.
Implementation:
1. Absolute Value Addition:
- If the most significant bits (MSBs) of `a` and `b` are the same (both positive or both negative), their absolute values are added.
- The MSB of the result is set to match the MSBs of `a` and `b` (sign bit remains consistent).
2. Absolute Value Subtraction:
- If the MSBs of `a` and `b` are different (one is positive, the other negative), the larger absolute value is determined.
- If `a` is greater than `b`, the result is `a - b` and the MSB of the result is set to 0 (positive).
- If `b` is greater than `a`, the result is `b - a`. The MSB of the result is set according to whether the result is zero or negative.
3. Precision:
- The operands `a` and `b` consist of integer and fractional parts, with the fractional part determined by parameter `Q`.
- The precision is consistent across both inputs and the output to ensure accurate fixed-point arithmetic.
4. Overflow Handling:
- Overflow is managed internally by observing the MSB to ensure the result fits within the N-bit range.
Give me the complete code. | false | true | false | fixed_point_adder | fixed_point_adder | [
"testbench_output_standardization"
] |
fixed_point_substractor | Please act as a professional Verilog designer.
Implement a module of a fixed-point subtractor for precise arithmetic operations with fixed precision.
Module name:
fixed_point_subtractor
Parameterized values:
Q: Represents the number of fractional bits in the fixed-point representation.
N: Represents the total number of bits (both integer and fractional) used for inputs and outputs.
Input ports:
a [N-1:0]: First N-bit fixed-point input operand.
b [N-1:0]: Second N-bit fixed-point input operand.
Output ports:
c [N-1:0]: N-bit output representing the result of the fixed-point subtraction.
Internal registers:
res [N-1:0]: N-bit register used to store the result of the subtraction operation.
Implementation:
Same Sign Subtraction: When the signs of a and b are the same, their fractional and integer parts are subtracted. The sign of the result will be the same as the inputs.
Different Sign Subtraction:
If a is positive and b is negative, the absolute values of a and b are added. The result will have a positive sign if a is greater than b, and a negative sign otherwise.
If a is negative and b is positive, the same logic applies, with the result's sign depending on the relative sizes of a and b.
Handling Zero:
When the result is zero, the sign bit is explicitly set to 0 to handle this edge case.
Precision:
The fixed-point precision is defined by the parameters Q (fractional bits) and N (total bits). This ensures that the subtraction is performed accurately while maintaining the necessary precision for both integer and fractional parts.
Give me the complete code. | false | true | false | fixed_point_subtractor | fixed_point_subtractor | [
"testbench_output_standardization"
] |
float_multi | Please act as a professional Verilog designer.
Implement a module of a 32-bit floating-point multiplier for IEEE-754 standard single-precision arithmetic.
The float_multi module is designed to perform high-precision multiplication of 32-bit single-precision floating-point numbers, following the IEEE 754 standard. This module enables accurate arithmetic operations essential for various computational applications.
Module name:
float_multi
Input ports:
clk (input): Clock signal for synchronization.
rst (input): Reset signal (active high).
a (input [31:0]): First operand in IEEE 754 format.
b (input [31:0]): Second operand in IEEE 754 format.
Output ports:
z (output reg [31:0]): Result of the multiplication in IEEE 754 format.
Internal signals:
counter (reg [2:0]): Cycle counter for operation sequencing.
a_mantissa, b_mantissa, z_mantissa (reg [23:0]): Mantissas of input and output numbers.
a_exponent, b_exponent, z_exponent (reg [9:0]): Exponents of input and output numbers.
a_sign, b_sign, z_sign (reg): Sign bits for inputs and output.
product (reg [49:0]): Intermediate product of the mantissas.
guard_bit, round_bit, sticky (reg): Rounding control bits.
Implementation:
-Initialization: The counter is reset to zero on the rst signal.
-Input Processing: The mantissas, exponents, and sign bits of inputs a and b are extracted during the first clock cycle.
-Special Cases Handling: The module identifies special cases like NaN (Not a Number) and infinity based on the inputs.
-Normalization: Mantissas are normalized if needed.
-Multiplication: The mantissas are multiplied, combining the signs and adjusting the exponents.
-Rounding and Adjustment: The module rounds the result and adjusts the exponent to ensure accurate representation.
-Output Generation: The final result is formatted in IEEE 754 standard, addressing overflow and underflow scenarios.
Give me the complete code. | false | true | false | float_multi | float_multi | [
"testbench_output_standardization"
] |
freq_div | Please act as a professional verilog designer.
Implement a frequency divider that the input clock frequency of 100MHz signal, and the outputs are 3 clock frequencies: 50MHz, 10MHz, 1MHz.
Module name:
freq_div
Input ports:
clk: Input clock signal
RST: Reset signal
Output ports:
CLK_50: Output clock signal with a frequency of clk divided by 2.
CLK_10: Output clock signal with a frequency of clk divided by 10.
CLK_1: Output clock signal with a frequency of clk divided by 100.
Implementation:
The module uses three counters to divide the input clock frequency.
CLK_50 generation:
On every positive edge of clk or RST, if RST is active, CLK_50 is set to 0.
Otherwise, CLK_50 is toggled by inverting its current value.
CLK_10 generation:
On every positive edge of clk or RST, if RST is active, CLK_10 is set to 0, and the counter cnt_10 is reset to 0.
If the counter cnt_10 reaches a value of 4, CLK_10 is toggled by inverting its current value, and the counter cnt_10 is reset to 0.
Otherwise, the counter cnt_10 is incremented by 1.
CLK_1 generation:
On every positive edge of clk or RST, if RST is active, CLK_1 is set to 0, and the counter cnt_100 is reset to 0.
If the counter cnt_100 reaches a value of 49, CLK_1 is toggled by inverting its current value, and the counter cnt_100 is reset to 0.
Otherwise, the counter cnt_100 is incremented by 1.
Give me the complete code. | true | true | true | freq_div | freq_div | [
"golden_signal_name_normalization",
"known_clk_case_unification",
"testbench_output_standardization"
] |
freq_divbyeven | Please act as a professional verilog designer.
Frequency divider that divides the input clock frequency by even numbers. This module generates a divided clock signal by toggling its output every specified number of input clock cycles.
Module name:
freq_diveven
Input ports:
clk: Input clock signal that will be divided.
rst_n: Active-low reset signal to initialize the module.
Output ports:
clk_div: Divided clock output signal.
Implementation:
The frequency divider uses a counter (`cnt`) to count the number of clock cycles. The `NUM_DIV` parameter specifies the division factor, which must be an even number.
- When the reset signal (`rst_n`) is low, the counter and the divided clock signal (`clk_div`) are initialized to zero.
- On each positive edge of the input clock (`clk`), if the counter is less than half of `NUM_DIV - 1`, the counter increments without changing the divided clock output.
- When the counter reaches the specified limit, it resets to zero and toggles the `clk_div` output signal, effectively dividing the frequency of the input clock by the even number specified by `NUM_DIV`.
Counter:
- The counter is a 4-bit register (`cnt`) that tracks the number of clock cycles.
Give me the complete code. | false | true | false | freq_divbyeven | freq_divbyeven | [
"testbench_output_standardization"
] |
freq_divbyfrac | Please act as a professional Verilog designer.
A frequency divider that divides the input clock frequency by fractional values. It generates a clock signal with a fractional frequency division (3.5x), using the double-edge clocking technique to achieve half-integer division while adjusting for duty cycle imbalance. By dividing uneven clock cycles and phase-shifting them, a smooth fractional clock output is produced.
Module name:
freq_divbyfrac
Input ports:
clk: Input clock signal.
rst_n: Active low reset signal to initialize the module.
Output ports:
clk_div: Fractionally divided clock output.
Implementation:
The module performs fractional frequency division by counting clock cycles and generating an intermediate divided clock signal. For 3.5x division:
The counter cycles through 7 clock cycles (MUL2_DIV_CLK = 7).
It generates two uneven clock periods: one with 4 source clock cycles and another with 3 source clock cycles.
In the next cycle, phase-shifted versions of the divided clock are generated. One phase is delayed by half a clock period, and the other is advanced by half a clock period.
Finally, the two intermediate clocks are logically OR-ed to produce the final fractional divided clock output, ensuring the divided clock signal has a uniform period.
Give me the complete code. | false | true | false | freq_divbyfrac | freq_divbyfrac | [
"golden_signal_name_normalization",
"testbench_output_standardization"
] |
freq_divbyodd | Please act as a professional verilog designer.
A frequency divider that divides the input clock frequency by odd numbers. The module generates a divided clock output by an odd divisor value provided as a parameter.
Module name:
freq_divbyodd
Input ports:
clk: Input clock signal.
rst_n: Active low reset signal that initializes the divider.
Output ports:
clk_div: Divided clock output.
Implementation:
The module divides the input clock frequency by an odd number defined by the parameter NUM_DIV, which defaults to 5.
Two counters, cnt1 and cnt2, are used for tracking the rising and falling edges of the clock. Each counter counts up to NUM_DIV - 1.
Two separate clock dividers, clk_div1 and clk_div2, are used for positive and negative edges of the clock, respectively. These are toggled when the counters reach half of NUM_DIV.
The final divided clock output, clk_div, is derived by logically OR-ing clk_div1 and clk_div2 to account for both clock edges.
The active low reset signal rst_n initializes the counters and the clock divider outputs.
Give me the complete code. | false | true | false | freq_divbyodd | freq_divbyodd | [
"testbench_output_standardization"
] |
fsm | Please act as a professional verilog designer.
Implement a Mealy FSM detection circuit that detects a single-bit input IN. When the input is 10011, output MATCH is 1, and MATCH is 0 in other cases. Support for continuous input and loop detection.
Module name:
fsm
Input ports:
IN: Input signal to the FSM.
clk: Clock signal used for synchronous operation.
RST: Reset signal to initialize the FSM.
Output ports:
MATCH: Output signal indicating a match condition based on the FSM state.
Implementation:
The module implements an FSM detection.
On every change in the input signal (IN) or positive edge of clk or RST, if RST is active, the output signal MATCH is set to 0.
If the sequence of inputs IN is 1, 0, 0, 1, 1, the MATCH signal is 1 at the same time as the last occurrence of IN=1. If the sequence of inputs IN is 1, 0, 0, 1, 1, 0, 0, 1, 1, the MATCH signal becomes 1 at the fifth and ninth of IN; otherwise, it is set to 0.
Give me the complete code. | true | true | true | verified_fsm | fsm | [
"golden_signal_name_normalization",
"known_clk_case_unification",
"module_name_alignment",
"spec_case_normalization",
"testbench_output_standardization"
] |
instr_reg | Please act as a professional Verilog designer.
An instruction register module designed to hold and process CPU instructions. It captures incoming instructions from various sources and separates them into distinct fields for further processing.
Module name:
instr_reg
Input ports:
clk: Clock signal for synchronization.
rst: Active low reset signal to initialize the register.
fetch [1:0]: Control signal indicating the source of the instruction (1 for register, 2 for RAM/ROM).
data [7:0]: 8-bit data input representing the instruction to be fetched.
Output ports:
ins [2:0]: High 3 bits of the instruction, indicating the opcode or operation.
ad1 [4:0]: Low 5 bits of the instruction, representing the register address.
ad2 [7:0]: The full 8-bit data from the second source.
Implementation:
The instruction register contains two 8-bit registers (ins_p1 and ins_p2) to store instructions from different sources.
On the rising edge of the clock (clk), if the reset (rst) signal is low, both registers are initialized to zero.
Based on the fetch signal:
If fetch is 2'b01, the instruction is fetched from the data input into ins_p1.
If fetch is 2'b10, the instruction is fetched from the data input into ins_p2.
If neither condition is met, the previous values in both registers are retained.
The outputs ins, ad1, and ad2 are derived from the stored instructions.
Give me the complete code. | false | true | false | instr_reg | instr_reg | [
"testbench_output_standardization"
] |
multi_16bit | Please act as a professional verilog designer.
Implement the design of an unsigned 16-bit multiplier. It utilizes shift and accumulate operations to generate the product output (yout). The module also includes control signals such as clock (clk), reset (rst_n), and start (start), along with a completion flag (done) indicating the completion of the multiplication operation.
Module name:
multi_16bit
Input ports:
clk: Chip clock signal.
rst_n: Active-low reset signal. Defined as 0 for chip reset and 1 for reset signal inactive.
start: Chip enable signal to initiate the multiplication operation.
ain: Input signal representing the multiplicand (a) with a data width of 16 bits.
bin: Input signal representing the multiplier (b) with a data width of 16 bits.
Output ports:
yout: Product output signal with a data width of 32 bits.
done: Chip output flag signal. Defined as 1 indicates the completion of the multiplication operation.
Implementation:
Data bit control:
On every positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the shift count register (i) is updated.
If the reset signal (rst_n) is low, indicating a reset condition, the shift count register (i) is set to 0.
If the start signal is active (start) and the shift count register (i) is less than 17, the shift count register (i) increments by 1.
If the start signal is inactive (!start), the shift count register (i) is reset to 0.
Multiplication completion flag generation:
On every positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the multiplication completion flag (done_r) is updated.
If the reset signal (rst_n) is low, the multiplication completion flag (done_r) is set to 0.
If the shift count register (i) is equal to 16, indicating the completion of the multiplication operation, the multiplication completion flag (done_r) is set to 1.
If the shift count register (i) is equal to 17, the multiplication completion flag (done_r) is reset to 0.
Shift and accumulate operation:
On every positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the module performs the shift and accumulate operation.
If the reset signal (rst_n) is low, indicating a reset condition, the multiplicand register (areg), multiplier register (breg), and product register (yout_r) are reset to 0.
If the start signal is active (start), the module starts the multiplication operation.
When the shift count register (i) is 0, the multiplicand (ain) and multiplier (bin) are stored in the respective registers (areg and breg).
For shift counts greater than 0 and less than 17, if the bit at position i-1 in the multiplicand register (areg) is high, the product register (yout_r) accumulates the shifted value of the multiplier register (breg) by shifting it left by i-1 positions and appending zeros at the least significant bit positions.
Output assignment:
The product output (yout) is assigned the value of the product register (yout_r).
Give me the complete code. | false | true | true | verified_multi_16bit | multi_16bit | [
"module_name_alignment",
"testbench_output_standardization"
] |
multi_8bit | Please act as a professional Verilog designer.
Implement a module of an 8-bit multiplier based on shifting and adding operations.
Module name:
multi_8bit
Input ports:
A [7:0]: First 8-bit input operand (representing a multiplicand).
B [7:0]: Second 8-bit input operand (representing a multiplier).
Output ports:
product [15:0]: 16-bit output representing the product of the two 8-bit inputs (A * B).
Implementation:
Multiplication: The module performs multiplication of A and B using the shift-and-add method.
- The algorithm iterates through each bit of the multiplier (B). For each bit that is set (1), the multiplicand (A) is added to the product at the corresponding shifted position.
- The process continues until all bits of the multiplier have been processed.
Shifting: After each addition, the multiplicand is logically shifted left by one bit to prepare for the next addition, simulating the traditional multiplication process.
The final product is stored in the output port, which is 16 bits wide to accommodate the maximum possible product of two 8-bit numbers.
Give me the complete code. | false | true | false | multi_8bit | multi_8bit | [
"testbench_output_standardization"
] |
multi_booth_8bit | Please act as a professional verilog designer.
Implement an 8-bit Radix-4 booth multiplier that performs the multiplication of two 8-bit inputs (a and b) using the Booth algorithm. It utilizes a clock signal (clk), and a reset signal (reset), and provides the product output (p) and a ready signal (rdy). The ready signal (rdy) is set to 1 to indicate the completion of the multiplication process.
Module name:
multi_booth_8bit
Input ports:
clk: Clock signal used for synchronous operation.
reset: Reset signal used to initialize the multiplier module.
a: 8-bit input representing the multiplicand.
b: 8-bit input representing the multiplier.
Output ports:
p: 16-bit output representing the product of the multiplication.
rdy: Ready signal indicating the completion of the multiplication operation.
Implementation:
On the positive edge of the clock signal (clk) or the positive edge of the reset signal (reset), the module performs the multiplication process.
If the reset signal (reset) is high, two 16-bit registers multiplier <= {{8{a[7]}}, a} and multiplicand <= {{8{b[7]}}, b}.
If the reset signal (reset) is low, indicating normal operation, the module checks if the counter (5bit ctr) is less than 16.
If the counter (ctr) is less than 16, the multiplicand register (multiplicand) is left-shifted by 1 to simulate the Booth algorithm's shifting operation.
If the current bit of the multiplier register (multiplier[ctr]) is 1, indicating a positive Booth encoding, the product register (p) accumulates the value of the multiplicand register (multiplicand).
The counter (ctr) is incremented by 1. Once the counter (ctr) reaches 16, indicating the completion of the multiplication process, the ready signal (rdy) is set to 1.
Give me the complete code. | false | true | true | verified_multi_booth_8bit | multi_booth_8bit | [
"module_name_alignment"
] |
multi_pipe_4bit | Please act as a professional verilog designer.
Implement the design of 4bit unsigned number pipeline multiplier. It consists of two levels of registers to store intermediate values and control the multiplication process.
Module name:
multi_pipe_4bit
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for chip reset and 1 for reset signal inactive.
mul_a: Input signal representing the multiplicand with a data width of "size" bits.
mul_b: Input signal representing the multiplier with a data width of "size" bits.
Output ports:
mul_out: Product output signal with a data width of 2*size bits.
Parameter:
size = 4
Implementation:
Extension of input signals:
The input signals (mul_a and mul_b) are extended by adding "size" number of zero bits at the most significant bit positions.
Multiplication operation:
The module uses a generate block to perform multiplication for each bit position of the multiplier (mul_b) and generate the partial products.
For each bit position i from 0 to size-1, the partial product is calculated as follows:
If the corresponding bit in the multiplier is 1, the multiplicand is left-shifted by i positions.
If the corresponding bit in the multiplier is 0, the partial product is set to 0 ('d0).
Add of partial products:
The module uses registers to store the intermediate sum values.
On the positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the module performs add operations.
If the reset signal (rst_n) is low, indicating a reset condition, the registers are set to 0.
If the reset signal (rst_n) is high, the registers are updated with the sum of the corresponding partial products.
Final product calculation:
On the positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the module calculates the final product.
If the reset signal (rst_n) is low, indicating a reset condition, the product output (mul_out) is set to 0.
If the reset signal (rst_n) is high, the product output (mul_out) is updated with the sum of registers.
Give me the complete code. | false | true | true | verified_multi_pipe | multi_pipe_4bit | [
"module_name_alignment",
"testbench_output_standardization"
] |
multi_pipe_8bit | Please act as a professional verilog designer.
Implement the design of unsigned 8bit multiplier based on pipelining processing. It utilizes a clock signal (clk), an active-low reset signal (rst_n), an input enable signal (mul_en_in), and provides an output enable signal (mul_en_out) and the product output (mul_out) of size 16 bits.
Module name:
multi_pipe_8bit
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for chip reset and 1 for reset signal inactive.
mul_en_in: Input enable signal that controls the multiplication operation.
mul_a: Input signal representing the multiplicand with a data width of 8 bits.
mul_b: Input signal representing the multiplier with a data width of 8 bits.
Output ports:
mul_en_out: Output enable signal indicating if the multiplication operation is enabled.
mul_out: Product output signal with a data width of 16 bits.
Implementation:
The module utilizes a pipeline architecture to improve performance. It consists of several key components:
Input Control:
The module includes an input enable signal, mul_en_in, which controls the multiplication operation.
On the positive edge of the clock signal, the module samples the input enable signal and stores it in a register, mul_en_out_reg.
The output enable signal, mul_en_out, is derived from the most significant bit of mul_en_out_reg, indicating whether the multiplication operation is enabled.
Input Registers:
The module includes registers, mul_a_reg and mul_b_reg, to store the input multiplicand and multiplier, respectively.
On the positive edge of the clock signal, the module samples the input values and stores them in the corresponding registers.
The registers are only updated when the input enable signal is active.
Partial Product Generation:
The module generates partial products by performing bitwise operations between the multiplicand and the individual bits of the multiplier.
It uses conditional assignments to select the appropriate bits from the multiplicand based on the multiplier bits.
The partial products are stored in a set of wires, temp, with each wire representing a different bit position.
Partial Sum Calculation:
The module performs addition operations on the partial products to calculate partial sums.
It uses a set of registers, sum, to store the intermediate sum values.
Each register corresponds to a group of partial products and is updated on the positive edge of the clock signal.
Final Product Calculation:
The module sums up all the partial sums to obtain the final product.
It uses a register, mul_out_reg, to store the accumulated sum.
On the positive edge of the clock signal, the register is updated with the sum of all partial sums.
Output Assignment:
The module assigns the output product value, mul_out, based on the output enable signal and the value in mul_out_reg.
If the output enable signal is active, indicating a valid product, the value in mul_out_reg is assigned to mul_out.
Otherwise, mul_out is set to 0.
Give me the complete code. | false | true | true | verified_multi_pipe_8bit | multi_pipe_8bit | [
"module_name_alignment",
"testbench_output_standardization"
] |
parallel2serial | Please act as a professional verilog designer.
Implement a module for parallel-to-serial conversion, where every four input bits are converted to a serial one bit output (from MSB to LSB). The output signal valid_out is set to 1 to indicate the availability of valid serial output. When valid_out = 1, the most significant bit of d is output, and the remaining three bits are output sequentially in the following 3 cycles.
Module name:
parallel2serial
Input ports:
clk: Clock signal used for synchronous operations.
rst_n: Reset signal. Defined as 0 for reset and 1 for reset signal inactive.
d: 4-bit parallel data input.
Output ports:
valid_out: Valid signal indicating the availability of serial output.
dout: Serial output representing the converted data.
Implementation:
The most significant bit of the parallel input is assigned to the serial output (dout). On each clock cycle, if the counter (cnt) is 3, indicating the last bit of the parallel input, the module updates the data register (data) with the parallel input (d), resets the counter (cnt) to 0, and sets the valid signal (valid) to 1.
Otherwise, the module increments the counter (cnt) by 1, sets the valid signal (valid) to 0, and shifts the data register (data) one bit to the left, with the most significant bit shifted to the least significant bit.
Counter Register: If the reset signal (rst_n) is high, the register (cnt) is incremented by 1.
Give me the complete code. | false | true | true | verified_parallel2serial | parallel2serial | [
"module_name_alignment",
"testbench_output_standardization"
] |
pe | Please act as a professional verilog designer.
Implement a Multiplying Accumulator for 32bit integer. In the MAC_PE, there is a register that stores the partial sum (the intermediate accumulation result), and in each cycle, the result of “a multiplied by b” will be accumulated in this register, and the “c” shows the value of the register.
Module name:
pe
Input ports:
clk: Clock signal used for synchronous operations.
rst: Reset signal. Defined as 1 for reset and 0 for reset signal inactive.
a: 32-bit input operand A.
b: 32-bit input operand B.
Output ports:
c: 32-bit output representing the accumulated result.
Implementation:
The module implements a parallel multiplier and accumulator using registers and an always block. It multiplies the input operands and accumulates the result into an output register.
Accumulator Register:
The module includes a register, c, to store the accumulated result.
On the positive edge of the clock signal (clk) or the positive edge of the reset signal (rst), the module updates the register.
If the reset signal (rst) is high, indicating a reset condition, the register (c) is set to 0. If the reset signal (rst) is low, the register (c) is updated by adding the product of the input operands (a and b) to its current value.
Multiplication and Accumulation:
Inside the always block, the module performs the multiplication and accumulation operation. If the reset signal (rst) is high, the register (c) is set to 0. If the reset signal (rst) is low, the module adds the product of the input operands (a and b) to the register (c).
Give me the complete code. | false | true | true | verified_pe | pe | [
"module_name_alignment",
"testbench_output_standardization"
] |
pulse_detect | Please act as a professional verilog designer.
Implement a module for pulse detection. The 1-bit input signal data_in is a continuous input, which is triggered by clk. When "data_in" changes from 0 to 1 to 0(3 cycles), this is considered as a "pulse". The indicating signal dataout is 1 at the end cycle of the "pulse", and then returns to 0 until the corresponding pulse appears again. For example, if data_in is 01010(5 cycles), the data_out is 00101.
Module name:
pulse_detect
Input ports：
clk: Clock signal.
rst_n: Reset signal (active low).
data_in: One-bit input signal.
Output ports：
data_out: Output signal indicating the presence of pulses.
Implementation:
Declare the module pulse_detect with input and output ports as specified in the ports statement.
Declare a register state to keep track of the current state of the pulse detection process.
Inside an always block, sensitive to the positive edge of the clk signal and the negative edge of the rst_n signal, implement the logic for pulse detection and output generation.
In the reset condition (~rst_n), set the state register to the initial state and set the data_out output to 0, indicating no pulse. Continue the detection process for the remaining states. For each state, check the value of data_in and transition to the next state accordingly. If the current state satisfies the last state of a "pulse", set data_out to 1, indicating the end of a pulse. Otherwise, set data_out to 0.
Give me the complete code. | false | true | true | verified_pulse_detect | pulse_detect | [
"module_name_alignment",
"testbench_output_standardization"
] |
radix2_div | Please act as a professional verilog designer.
Implement a simplified radix-2 divider on 8-bit signed or unsigned integers. and the inputs are two 8-bit operands. The module accepts a dividend and a divisor as inputs and provides a 16-bit result containing both the quotient and the remainder. The design supports both signed and unsigned division operations.
Module name:
radix2_div
Input ports:
clk: Clock signal used for synchronous operation.
rst: The reset signal to initialize or reset the module.
sign: 1-bit indicates if the operation is signed (1) or unsigned (0).
dividend: 8-bit input signal representing the dividend for division.
divisor: 8-bit input signal representing the divisor for division.
opn_valid: 1-bit indicates that a valid operation request is present.
Output ports:
res_valid: 1-bit output signal indicating the result is valid and ready.
result: 16-bit the output containing the remainder in the upper 8 bits and the quotient in the lower 8 bits.
Implementation:
Operation Start:
When opn_valid is high and res_valid is low, the module saves the inputs dividend and divisor.
Initializes the shift register SR with the absolute value of the dividend shifted left by one bit.
Sets NEG_DIVISOR to the negated absolute value of the divisor.
Sets the counter cnt to 1 and start_cnt to 1 to begin the division process.
Division Process(If start_cnt is high, the module performs the following steps):
If the counter cnt reaches 8 (most significant bit of cnt is set), the division is complete:
cnt and start_cnt are cleared.
Updates the shift register SR with the final remainder and quotient.
Otherwise, the counter cnt is incremented, and the shift register SR is updated based on the subtraction result:
Computes the subtraction of NEG_DIVISOR.
Uses a multiplexer to select the appropriate result based on the carry-out.
Updates SR by shifting left and inserting the carry-out.
Result Validity:
res_valid is managed based on the reset signal, the counter, and whether the result has been consumed.
Give me the complete code. | false | true | true | verified_radix2_div | radix2_div | [
"module_name_alignment",
"testbench_output_standardization"
] |
right_shifter | Please act as a professional verilog designer.
Implement a right shifter. The module performs an 8-bit right shift on a 1-bit input by first initializing the q register to 0. On each rising edge of the clock, the module shifts the contents of the q register to the right by one bit and inserts the new input bit d into the most significant position of the register.
Module name:
right_shifter
Input ports:
clk: Clock signal used for synchronous operation.
d: Input signal to be right-shifted.
Output ports:
q: Output signal representing the result of the right shift operation.
Implementation:
The register is defined as reg [7:0] q and initialized to 0 using the initial statement. The value of q is right-shifted by 1 bit using the >> operator: q <= (q >> 1).
The most significant bit (q[7]) of the register is assigned the value of the input signal (d): q[7] <= d.
Give me the complete code. | false | true | true | verified_right_shifter | right_shifter | [
"module_name_alignment",
"testbench_output_standardization"
] |
ring_counter | Please act as a professional Verilog designer.
Implement a module of an 8-bit ring counter for cyclic state sequences.
Module name:
ring_counter
Input ports:
clk: Clock signal that drives the state transitions of the ring counter.
reset: Reset signal to initialize the counter to its starting state.
Output ports:
out [7:0]: 8-bit output representing the current state of the ring counter. Only one bit is set high at any time, and the set bit cycles through the 8-bit output.
Internal logic:
1. State Transition: The ring counter follows a cyclic pattern where exactly one bit is set to 1 in the output at any given time, and the 1 shifts to the next bit with each clock pulse.
2. Initialization: When the reset signal is high, the counter is initialized to its starting state, typically with the least significant bit (LSB) of out set to 1 (i.e., out = 8'b0000_0001).
3. Cycling Behavior: On each rising edge of the clock signal, the 1 shifts to the next bit in the sequence, and after reaching the most significant bit (MSB), it wraps around to the LSB, creating a cyclic sequence.
Reset Behavior: When reset is high, the ring counter is reset to its initial state (out = 8'b0000_0001).
Give me the complete code. | false | true | false | ring_counter | ring_counter | [
"testbench_output_standardization"
] |
sequence_detector | Please act as a professional Verilog designer.
Implement a module of a sequence detector to detect a specific 4-bit binary sequence 1001.
Module name:
sequence_detector
Input ports:
clk: Clock signal to synchronize the detector.
reset_n: Reset signal to initialize the state machine.
data_in: 1-bit binary input signal to feed the bitstream for sequence detection.
Output ports:
sequence_detected: 1-bit output signal that is set high when the specific sequence is detected.
Internal logic:
State Machine: The sequence detector uses a finite state machine (FSM) with the following states:
IDLE: Waiting for the start of the sequence.
S1: The first bit of the desired sequence is detected.
S2: The second bit of the desired sequence is detected.
S3: The third bit of the desired sequence is detected.
S4: The fourth and final bit of the desired sequence is detected, and the output sequence_detected is set high.
Implementation:
-FSM Design: The FSM transitions through states based on the bitstream data_in. On each clock cycle, the detector checks for a match of the specific sequence.
-Sequence Detection: The module checks the input data_in and transitions between states. Once the complete sequence is detected, sequence_detected is asserted.
-Reset Behavior: When reset is high, the state machine returns to the IDLE state, resetting the detection process. | false | true | false | sequence_detector | sequence_detector | [
"testbench_output_standardization"
] |
serial2parallel | Please act as a professional verilog designer.
Implement a series-parallel conversion circuit. It receives a serial input signal "din_serial" along with a control signal "din_valid" indicating the validity of the input data. The module operates on the rising edge of the clock signal "clk" and uses a synchronous design. The input din_serial is a single-bit data, and when the module receives 8 input data, the output dout_parallel outputs the 8-bit data(The serial input values are sequentially placed in dout_parallel from the most significant bit to the least significant bit), and the dout_valid is set to 1.
Module name:
serial2parallel
Input ports:
clk: Clock signal.
rst_n: Reset signal (active low).
din_serial: Serial input data.
din_valid: Validity signal for input data.
Output ports:
dout_parallel: Parallel output data (8 bits wide).
dout_valid: Validity signal for the output data.
Implementation:
The module utilizes a 4-bit counter (cnt) to keep track of the number of serial input data bits received. Every eight din_serial input, dout_parallel will output. When all 8 serial data bits have been received, the valid output signal is set to 1, indicating that the parallel output data is valid. Otherwise, the valid output signal is set to 0, indicating that the parallel output data is not valid.
Give me the complete code. | false | true | true | verified_serial2parallel | serial2parallel | [
"module_name_alignment",
"testbench_output_standardization"
] |
signal_generator | Please act as a professional verilog designer.
Implement a Triangle Wave signal generator module that generates a waveform by incrementing and decrementing a 5-bit signal named "wave". The waveform cycles between 0 and 31, which is incremented or decremented by 1.
Module name:
signal_generator
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for reset and 1 for reset signal inactive.
Output ports:
wave: 5-bit output waveform signal representing the generated waveform.
Implementation:
State and Waveform Generation:
The module includes a register, state, used to control the state of the waveform generation.
The module also includes a register, wave, with a width of 5 bits, which represents the generated waveform.
The state and waveform registers are updated in the always block, triggered on the positive edge of the clock signal (posedge clk) or the negative edge of the reset signal (negedge rst_n).
On reset, indicated by ~rst_n, the state register is cleared to 0, and the wave register is cleared to 0.
The waveform generation is controlled using a case statement based on the current state:
If the state is 0, the waveform (wave) is incremented by 1.
If the waveform reaches 31 (wave == 31), the state is transitioned to 1.
If the state is 1, the waveform is decremented by 1.
If the waveform reaches 0 (wave == 0), the state is transitioned back to 0.
The waveform generation continues to cycle between 0 and 31 based on the state transitions.
Give me the complete code. | false | true | true | verified_signal_generator | signal_generator | [
"module_name_alignment",
"testbench_output_standardization"
] |
square_wave | Please act as a professional verilog designer.
The module is a simple yet effective generator designed to produce square wave signals with variable frequency. It takes an input clock signal and a frequency value, and outputs a square wave signal toggling at the specified frequency.
Module name:
square_wave
Input ports:
clk: Clock signal that drives the module.
[7:0]freq: Frequency control, specifying how often the square wave toggles.
Output ports:
wave_out: Square wave output signal.
Internal Registers:
count (reg [7:0]): Counter register used to track cycles between wave toggles.
Implementation:
Counter Operation:
The count register increments on each rising edge of the clk.
When count reaches (freq - 1), the count is reset to 0 and wave_out is toggled (i.e., flipped from 0 to 1 or from 1 to 0).
If count has not reached freq, it simply increments by one on the next clock cycle.
Square Wave Generation:
The module produces a square wave by flipping the wave_out signal at the rate determined by freq.
The higher the freq value, the slower the square wave toggles (i.e., the lower the output frequency), and vice versa.
Give me the complete code. | false | true | false | square_wave | square_wave | [
"testbench_output_standardization"
] |
sub_64bit | Please act as a professional Verilog designer.
Implement a module of a 64-bit subtractor with overflow checking for high-precision arithmetic operations.
Module name:
sub_64bit
Input ports:
A [63:0]: First 64-bit input operand (representing a large signed integer).
B [63:0]: Second 64-bit input operand (representing a large signed integer to be subtracted from A).
Output ports:
result [63:0]: 64-bit output representing the difference of the two operands (A - B).
overflow: 1-bit output indicating whether an overflow occurred during the subtraction operation.
Implementation:
Subtraction: The module performs binary subtraction of A and B to obtain the result.
Overflow Detection: The module checks for overflow conditions by examining the sign bits of A, B, and the result.
- Positive overflow occurs when a positive number (A) is subtracted by a negative number (B) and the result is negative.
- Negative overflow occurs when a negative number (A) is subtracted by a positive number (B) and the result is positive.
The overflow flag is set to 1 if an overflow condition is detected; otherwise, it is set to 0.
Give me the complete code. | false | true | false | sub_64bit | sub_64bit | [
"testbench_output_standardization"
] |
synchronizer | Please act as a professional verilog designer.
Implement a multi-bit MUX-based synchronizer, data_in will remain constant during the period when data_en is high, and data_en is high for at least 3 clk_b clock cycles. When the value of data_en is high, data can be synchronized. The data change frequency of data_in is very low. The change interval between two adjacent data is at least 10 clk_b clock cycles.
The clock clk_a is responsible for: input data_in is refer to clock a. enable signal data_en is refer to clock a.
The clock clk_b is responsible for the enable signal data_en delays two cycles, that is, two D flip-flops. This is done with reference to clock b. And the data is finally output dataout, and the output refers to clock b.
Module name:
synchronizer
Input ports:
clk_a: Clock signal A used for synchronous operations.
clk_b: Clock signal B used for synchronous operations.
arstn: Active-low reset signal A. Defined as 0 for reset and 1 for reset signal inactive.
brstn: Active-low reset signal B. Defined as 0 for reset and 1 for reset signal inactive.
data_in: Input data signal of size 4 bits.
data_en: Input enable signal that controls the selection operation.
Output ports:
dataout: Output data signal of size 4 bits.
Implementation:
Data Register:
The module includes a register, data_reg, to store the input data signal, data_in.
On the positive edge of clock signal A (clk_a) or the falling edge of reset signal A (arstn), the module updates the register. If the reset signal A (arstn) is low, indicating a reset condition, the register (data_reg) is set to 0. If the reset signal A (arstn) is high, the register (data_reg) is updated with the input data signal (data_in).
Enable Data Register:
The module includes a register, en_data_reg, to store the input enable signal, data_en.
On the positive edge of clock signal A (clk_a) or the falling edge of reset signal A (arstn), the module updates the register. If the reset signal A (arstn) is low, the register (en_data_reg) is set to 0. If the reset signal A (arstn) is high, the register (en_data_reg) is updated with the input enable signal (data_en).
Enable Control Registers:
The module includes two registers, en_clap_one and en_clap_two, to control the selection of the input data. On the positive edge of clock signal B (clk_b) or the falling edge of reset signal B (brstn), the module updates the registers. If the reset signal B (brstn) is low, indicating a reset condition, both registers (en_clap_one and en_clap_two) are set to 0.
If the reset signal B (brstn) is high, the registers (en_clap_one and en_clap_two) are updated based on the value of en_data_reg. The register en_clap_one is assigned the value of en_data_reg, and en_clap_two is assigned the previous value of en_clap_one.
Output Assignment:
On the positive edge of clock signal B (clk_b) or the falling edge of reset signal B (brstn), the module assigns the output data value. If the reset signal B (brstn) is low, indicating a reset condition, the output data (dataout) is set to 0. If the reset signal B (brstn) is high and the control signal (en_clap_two) is active, the output data (dataout) is assigned the value of the data register (data_reg). If the control signal (en_clap_two) is inactive, the output data (dataout) retains its previous value.
Give me the complete code. | false | true | true | verified_synchronizer | synchronizer | [
"module_name_alignment",
"testbench_output_standardization"
] |
traffic_light | Please act as a professional verilog designer.
Implement a traffic light, with red, yellow and green three small indicators and a pedestrian button, under normal circumstances, the motor vehicle lane indicator light according to 60 clock cycles of green, 5 clock cycles of yellow, 10 clock cycles of red. When the pedestrian button is pressed, if the remaining green time is greater than 10 clocks, it is shortened to 10 clocks, and if it is less than 10 clocks, it remains unchanged. The lane light and the sidewalk light should be paired, when the lane light is green or yellow, the sidewalk light is red; When the lane light is red, the sidewalk light is green, and for the sake of simplicity, only the lane light is considered.
Module name:
traffic_light
Inputs:
rst_n: Reset signal (active low).
clk: Clock signal.
pass_request: Request signal for allowing vehicles to pass.
Outputs:
clock[7:0]: An 8-bit output representing the count value of the internal counter.
red, yellow, green: Output signals representing the state of the traffic lights.
Parameters:
idle, s1_red, s2_yellow, s3_green: Enumeration values representing different states of the traffic light controller.
Registers and Wires:
cnt: A 8-bit register used as an internal counter for timing purposes.
state: A 2-bit register representing the current state of the traffic light controller.
p_red, p_yellow, p_green: 1-bit registers representing the next values for the red, yellow, and green signals.
Implementation:
The following is the design track we recommend:
The first always block is responsible for the state transition logic. It uses a case statement to handle different states. Here's a summary of each state:
idle: Initial state where all signals are set to 0. Transition to s1_red state occurs immediately.
s1_red: Sets the red signal to 1 and waits for a count of 3 before transitioning to s3_green state. Otherwise, it remains in s1_red state.
s2_yellow: Sets the yellow signal to 1 and waits for a count of 3 before transitioning to s1_red state. Otherwise, it remains in s2_yellow state.
s3_green: Sets the green signal to 1 and waits for a count of 3 before transitioning to s2_yellow state. Otherwise, it remains in s3_green state.
The second always block handles the counting logic of the internal counter (cnt). The counter is decremented by 1 on every positive edge of the clock or negative edge of the reset signal. The counter values are adjusted based on various conditions:
If (!rst_n), the counter is set to 10.
If the pass_request signal is active and the green signal is active, the counter is set to 10.
If the green signal is inactive and the previous green signal (p_green) was active, the counter is set to 60.
If the yellow signal is inactive and the previous yellow signal (p_yellow) was active, the counter is set to 5.
If the red signal is inactive and the previous red signal (p_red) was active, the counter is set to 10.
Otherwise, the counter is decremented normally.
The assign statement assigns the value of the internal counter (cnt) to the output clock.
The final always block handles the output signals. It assigns the previous values (p_red, p_yellow, p_green) to the output signals (red, yellow, green) on the positive edge of the clock or negative edge of the reset signal.
Give me the complete code. | false | true | true | verified_traffic_light | traffic_light | [
"module_name_alignment",
"testbench_output_standardization"
] |
up_down_counter | Please act as a professional Verilog designer.
Module name:
up_down_counter
Function:
A 16-bit counter that can increment or decrement based on control signals.
Input ports:
clk: Clock signal (1-bit), used to synchronize the counting process.
reset: Reset signal (1-bit), used to reset the counter to zero.
up_down: Control signal (1-bit), determines the counting direction.
If up_down = 1, the counter increments; if up_down = 0, it decrements.
Output ports:
count [15:0]: 16-bit output representing the current counter value.
Implementation:
The module uses a synchronous process triggered by the rising edge of the clock signal (`clk`).
If the reset signal (`reset`) is active, the counter resets to zero.
If the `up_down` control signal is high, the counter increments on each clock cycle.
If the `up_down` control signal is low, the counter decrements on each clock cycle.
The `count` output reflects the current value of the counter, which can range from 0 to 65535.
Give me the complete code. | false | true | false | up_down_counter | up_down_counter | [
"testbench_output_standardization"
] |
width_8to16 | Please act as a professional verilog designer.
Implement a data width conversion circuit that converts 8-bit data input to 16-bit data output. The module provides two output ports: valid_out, which indicates the validity of the output data, and data_out, which represents the converted 16-bit output data. The first arriving 8-bit data should be placed in the higher 8 bits of the 16-bit data output. The valid_out and data_out signals are generated in the next clock cycle after the two data inputs. When there is only one data input, valid_out and data_out are not generated immediately. Instead, they wait for the arrival of the next data input to complete the concatenation of the two data inputs before generating valid_out and data_out.
Module name:
width_8to16
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for reset and 1 for reset signal inactive.
valid_in: Input signal indicating the validity of the input data.
data_in: 8-bit input data to be converted.
Output ports:
valid_out: Output signal indicating the validity of the output data.
data_out: 16-bit output data resulting from the width conversion.
Implementation:
The data_out register is triggered on the positive edge of the clock signal (posedge clk) or the negative edge of the reset signal (negedge rst_n).
On reset, indicated by !rst_n, the data_out register is cleared to 0.
If the input data is valid (valid_in) and the flag signal is active, the data_out register is updated by concatenating the contents of the data_lock register (8 bits) and the data_in register (8 bits) to form a 16-bit output. The first valid data is temporarily stored, and when the second valid data is inputted, they are concatenated to produce the output valid_out and data_out.
Give me the complete code. | false | true | true | verified_width_8to16 | width_8to16 | [
"module_name_alignment",
"testbench_output_standardization"
] |
RTLLM Variants (Community Dataset Derivatives)
This repository hosts community-maintained derivative variants based on upstream RTLLM releases. It is intended for benchmarking reproducibility and evaluation workflow integration.
Important Notice
- This repository is not an official release from the RTLLM paper authors.
- Variants in this repository may include prompt wording normalization, interface naming unification, or testbench output standardization for evaluator consistency.
- For official benchmark content, refer to upstream RTLLM.
Upstream Reference
- Project: https://github.com/hkust-zhiyao/RTLLM
- RTLLM v2 baseline commit used by current variant pipeline:
41b26896e33b536940116a975626455eed3de65e
Available Variants
rtllm_v2_mod/converted/: benchmark layoutdelta_report.json: machine-readable differences vs upstream baselinemanifest.json: provenance and generation metadataREADME.md: variant-specific summary
Intended Usage
- Direct download via Hugging Face dataset API/CLI
- Reproducible benchmark evaluation pipelines that consume RTLLM-style folder structure
License
Each variant follows upstream licensing constraints and includes required license files where applicable.
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